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authorStefan Christ <s.christ@phytec.de>2016-05-04 15:25:57 +0200
committerSascha Hauer <s.hauer@pengutronix.de>2016-05-09 08:38:59 +0200
commitb66a106f3422b811f10e9b9dc987e2bc7f4fe449 (patch)
tree55a0213ca6d4d7d42d0857a9679e23be218b70d4 /common/blspec.c
parent9d5cf8d42709763d2607cde991e024f36600eb07 (diff)
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mci: imx-esdhc: implement reset quirks for i.MX6 DualLite/Solo
First of all the reset values of MMC interfaces are differently between Quad and DualLite/Solo SoM. Register VEND_SPEC2(0xC8) Quad: 0x0 DualLite: 0x00000006 default: 0x00000006 (from i.MX6 Reference Manual) Furthermore the ROM Code of Quad and DualLite uses the MMC interfaces differently when it loads the bootloader from that device: Register DLL_CTRL(0x60) Bit 25 FBCLK_SEL (0x48) Quad: 0x0 0 DualLite: 0x01000021 1 Since the linux kernel and barebox driver doesn't reset all registers, the MMC interface is in an inconsistent state, which leads to boot failures for some eMMC devices on the i.MX6 DualLite SoM. The errors look like: mmcblk3: error -110 sending stop command, original cmd response 0x900, card status 0x400900 mmcblk3: error -84 transferring data, sector 24578, nr 2, cmd response 0x900, card status 0x0 mmcblk3: retrying using single block read mmcblk3: error -84 transferring data, sector 24578, nr 2, cmd response 0x900, card status 0x0 blk_update_request: I/O error, dev mmcblk3, sector 24578 It's sufficient to reset register DLL_CTRL and bit FBCLK_SEL. Register VEND_SPEC2 has no effect. Signed-off-by: Stefan Christ <s.christ@phytec.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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