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| author | Sascha Hauer <s.hauer@pengutronix.de> | 2018-03-19 08:49:57 +0100 |
|---|---|---|
| committer | Sascha Hauer <s.hauer@pengutronix.de> | 2018-03-19 08:50:16 +0100 |
| commit | cad55edfb5838d53ec1eef38abff7be4b8a6143b (patch) | |
| tree | ab9aa0d0fd4e491018af1c84d15366fee9f7d236 /common | |
| parent | e37331820e94820e7825301f95308ab64aac35ca (diff) | |
| download | barebox-cad55edfb5838d53ec1eef38abff7be4b8a6143b.tar.gz barebox-cad55edfb5838d53ec1eef38abff7be4b8a6143b.tar.xz | |
ARM: AM335x: Fix invalid register access
Several DDR3 phy registers are written with the pattern x<<30 | x<<20 | x<<10 | x.
The x<<30 doesn't fit into 32bit which causes a compiler warning.
Looking at the reference manual only the lower 10bit of the registers
have any meaning, so drop the other bogus values. This affects the
registers:
AM33XX_DATA0_RD_DQS_SLAVE_RATIO_0
AM33XX_DATA0_WR_DQS_SLAVE_RATIO_0
AM33XX_DATA0_WR_DQS_SLAVE_RATIO_1
AM33XX_DATA0_WRLVL_INIT_RATIO_0
AM33XX_DATA0_GATELVL_INIT_RATIO_0
AM33XX_DATA0_GATELVL_INIT_RATIO_1
AM33XX_DATA0_FIFO_WE_SLAVE_RATIO_0
AM33XX_DATA0_WR_DATA_SLAVE_RATIO_0
(AM33XX_DATA0_WR_DQS_SLAVE_RATIO_1 and AM33XX_DATA0_GATELVL_INIT_RATIO_1
do not even exist according to the reference manual, but that's another
story.)
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'common')
0 files changed, 0 insertions, 0 deletions