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| author | Stefan Roese <sr@denx.de> | 2005-08-04 17:09:16 +0200 |
|---|---|---|
| committer | Stefan Roese <sr@denx.de> | 2005-08-04 17:09:16 +0200 |
| commit | 17f50f22bc3f2d17258523f2ef3074e6ce1f7ffa (patch) | |
| tree | 2c5d47cd55f487f0504458908d587e9bcd6963a6 /cpu/ppc4xx/405gp_enet.c | |
| parent | 3e0bc4473add883fd68a49b7dab971191b943415 (diff) | |
| download | barebox-17f50f22bc3f2d17258523f2ef3074e6ce1f7ffa.tar.gz barebox-17f50f22bc3f2d17258523f2ef3074e6ce1f7ffa.tar.xz | |
Add support for AMCC Bamboo PPC440EP eval board
Patch by Stefan Roese, 04 Aug 2005
Diffstat (limited to 'cpu/ppc4xx/405gp_enet.c')
| -rw-r--r-- | cpu/ppc4xx/405gp_enet.c | 27 |
1 files changed, 12 insertions, 15 deletions
diff --git a/cpu/ppc4xx/405gp_enet.c b/cpu/ppc4xx/405gp_enet.c index 9c17e31bd4..b60d1221d0 100644 --- a/cpu/ppc4xx/405gp_enet.c +++ b/cpu/ppc4xx/405gp_enet.c @@ -166,7 +166,6 @@ static void ppc_4xx_eth_halt (struct eth_device *dev) failsafe--; if (failsafe == 0) break; - } /* EMAC RESET */ @@ -223,18 +222,19 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis) #endif /* MAL RESET */ - mtdcr (malmcr, MAL_CR_MMSR); - /* wait for reset */ - while (mfdcr (malmcr) & MAL_CR_MMSR) { - }; + mtdcr (malmcr, MAL_CR_MMSR); + /* wait for reset */ + while (mfdcr (malmcr) & MAL_CR_MMSR) { + }; + #if defined(CONFIG_440_EP) || defined(CONFIG_440_GR) out32 (ZMII_FER, 0); udelay(100); /* set RII mode */ out32 (ZMII_FER, ZMII_RMII | ZMII_MDI0); #elif defined(CONFIG_440) - /* set RMII mode */ - out32 (ZMII_FER, ZMII_RMII | ZMII_MDI0); + /* set RMII mode */ + out32 (ZMII_FER, ZMII_RMII | ZMII_MDI0); #endif /* CONFIG_440 */ /* MAL Channel RESET */ @@ -324,14 +324,11 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis) (int) speed, (duplex == HALF) ? "HALF" : "FULL"); } -#if defined(CONFIG_440) - /* Errata 1.12: MAL_1 -- Disable MAL bursting */ - if( get_pvr() == PVR_440GP_RB) - mtdcr (malmcr, MAL_CR_OPBBL | MAL_CR_LEA | MAL_CR_PLBLT_DEFAULT); - else -#else mtdcr (malmcr, MAL_CR_PLBB | MAL_CR_OPBBL | MAL_CR_LEA | MAL_CR_PLBLT_DEFAULT); -#endif + /* Errata 1.12: MAL_1 -- Disable MAL bursting */ + if (get_pvr() == PVR_440GP_RB) { + mtdcr (malmcr, mfdcr(malmcr) & ~MAL_CR_PLBB); + } /* Free "old" buffers */ if (hw_p->alloc_tx_buf) @@ -418,6 +415,7 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis) reg |= dev->enetaddr[5]; out32 (EMAC_IAL + hw_p->hw_addr, reg); + switch (devnum) { #if defined(CONFIG_NET_MULTI) case 1: @@ -498,7 +496,6 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis) out32 (EMAC_RX_HI_LO_WMARK + hw_p->hw_addr, 0x0f002000); #endif - /* Frame gap set */ out32 (EMAC_I_FRAME_GAP_REG + hw_p->hw_addr, 0x00000008); |