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| author | Marian Balakowicz <m8@semihalf.com> | 2006-06-30 18:19:42 +0200 |
|---|---|---|
| committer | Marian Balakowicz <m8@semihalf.com> | 2006-06-30 18:19:42 +0200 |
| commit | f6e5739a68131998a5ae8aa0cf56a0316f810200 (patch) | |
| tree | 010b89799af2478323c7f1cc04665b51b5cc4e50 /cpu/ppc4xx/405gp_pci.c | |
| parent | f73e73ba0e422e6f79030d77286dd57becaee16f (diff) | |
| parent | 6c5879f380be38d85fef0d3aba3353358f4b2ff4 (diff) | |
| download | barebox-f6e5739a68131998a5ae8aa0cf56a0316f810200.tar.gz barebox-f6e5739a68131998a5ae8aa0cf56a0316f810200.tar.xz | |
Merge: Add support for AMCC 440SPe CPU based eval board (Yucca).
Diffstat (limited to 'cpu/ppc4xx/405gp_pci.c')
| -rw-r--r-- | cpu/ppc4xx/405gp_pci.c | 9 |
1 files changed, 7 insertions, 2 deletions
diff --git a/cpu/ppc4xx/405gp_pci.c b/cpu/ppc4xx/405gp_pci.c index fad895b319..0ccb3d81c6 100644 --- a/cpu/ppc4xx/405gp_pci.c +++ b/cpu/ppc4xx/405gp_pci.c @@ -438,7 +438,7 @@ void pci_440_init (struct pci_controller *hose) * The PCI initialization sequence enable bit must be set ... if not abort * pci setup since updating the bit requires chip reset. *--------------------------------------------------------------------------*/ -#if defined(CONFIG_440GX) || defined(CONFIG_440SP) +#if defined(CONFIG_440GX) || defined(CONFIG_440SP) || defined(CONFIG_440SPE) unsigned long strap; mfsdr(sdr_sdstp1,strap); @@ -502,7 +502,7 @@ void pci_440_init (struct pci_controller *hose) out16r( PCIX0_CLS, 0x00060000 ); /* Bridge, host bridge */ #endif -#if defined(CONFIG_440GX) +#if defined(CONFIG_440GX) || defined(CONFIG_440SPE) out32r( PCIX0_BRDGOPT1, 0x04000060 ); /* PLB Rq pri highest */ out32r( PCIX0_BRDGOPT2, in32(PCIX0_BRDGOPT2) | 0x83 ); /* Enable host config, clear Timeout, ensure int src1 */ #elif defined(PCIX0_BRDGOPT1) @@ -520,8 +520,13 @@ void pci_440_init (struct pci_controller *hose) out32r( PCIX0_POM0SA, 0 ); /* disable */ out32r( PCIX0_POM1SA, 0 ); /* disable */ out32r( PCIX0_POM2SA, 0 ); /* disable */ +#if defined(CONFIG_440SPE) + out32r( PCIX0_POM0LAL, 0x10000000 ); + out32r( PCIX0_POM0LAH, 0x0000000c ); +#else out32r( PCIX0_POM0LAL, 0x00000000 ); out32r( PCIX0_POM0LAH, 0x00000003 ); +#endif out32r( PCIX0_POM0PCIAL, CFG_PCI_MEMBASE ); out32r( PCIX0_POM0PCIAH, 0x00000000 ); out32r( PCIX0_POM0SA, 0xf0000001 ); /* 256MB, enabled */ |