diff options
| author | wdenk <wdenk> | 2004-04-18 23:32:11 +0000 |
|---|---|---|
| committer | wdenk <wdenk> | 2004-04-18 23:32:11 +0000 |
| commit | e35745bb64fae64da3e1fa7f4afe3213287f5908 (patch) | |
| tree | 492a81e51c1102c16ec8ad265fa218586ba523fb /cpu | |
| parent | 2471111d3511dab6b80e87bd5901be9fafa514db (diff) | |
| download | barebox-e35745bb64fae64da3e1fa7f4afe3213287f5908.tar.gz barebox-e35745bb64fae64da3e1fa7f4afe3213287f5908.tar.xz | |
* Temporarily disabled John Kerl's extended MII command code because
"miivals.h" is missing
* Patches by Mark Jonas, 13 Apr 2004:
- Remove CS0 chip select timing setting from cpu/mpc5xxx/start.S
- Add sync instructions to IceCube SDRAM init code
- Move SDRAM chip constants into seperate include files
- Unify DDR and SDR initialization code
- Unify all IceCube (Lite5xxx) target names
Diffstat (limited to 'cpu')
| -rw-r--r-- | cpu/mpc5xxx/start.S | 20 |
1 files changed, 8 insertions, 12 deletions
diff --git a/cpu/mpc5xxx/start.S b/cpu/mpc5xxx/start.S index 559c7f415a..e12eee9d1d 100644 --- a/cpu/mpc5xxx/start.S +++ b/cpu/mpc5xxx/start.S @@ -103,6 +103,9 @@ boot_cold: boot_warm: mfmsr r5 /* save msr contents */ + /* Move CSBoot and adjust instruction pointer */ + /*--------------------------------------------------------------*/ + #if defined(CFG_LOWBOOT) #if defined(CFG_RAMBOOT) #error CFG_LOWBOOT is incompatible with CFG_RAMBOOT @@ -113,19 +116,15 @@ boot_warm: stw r3, 0x4(r4) /* CS0 start */ lis r3, STOP_REG(CFG_BOOTCS_START, CFG_BOOTCS_SIZE)@h ori r3, r3, STOP_REG(CFG_BOOTCS_START, CFG_BOOTCS_SIZE)@l - stw r3, 0x8(r4) /* CS0 stop */ - lis r3, 0x00047800@h - ori r3, r3, 0x00047800@l - stw r3, 0x300(r4) /* set timing, CS0/boot conf reg */ lis r3, 0x02010000@h ori r3, r3, 0x02010000@l - stw r3, 0x54(r4) /* CS0 and Boot enable, IPBI ctrl reg */ + stw r3, 0x54(r4) /* CS0 and Boot enable */ - lis r3, lowboot_reentry@h - ori r3, r3, lowboot_reentry@l + lis r3, lowboot_reentry@h /* jump from bootlow address space (0x0000xxxx) */ + ori r3, r3, lowboot_reentry@l /* to the address space the linker used */ mtlr r3 - blr /* jump to flash based address */ + blr lowboot_reentry: lis r3, START_REG(CFG_BOOTCS_START)@h @@ -134,12 +133,9 @@ lowboot_reentry: lis r3, STOP_REG(CFG_BOOTCS_START, CFG_BOOTCS_SIZE)@h ori r3, r3, STOP_REG(CFG_BOOTCS_START, CFG_BOOTCS_SIZE)@l stw r3, 0x50(r4) /* Boot stop */ - lis r3, 0x00047800@h - ori r3, r3, 0x00047800@l - stw r3, 0x300(r4) /* set timing, CS0/boot conf reg */ lis r3, 0x02000001@h ori r3, r3, 0x02000001@l - stw r3, 0x54(r4) /* Boot enable, CS0 disable, wait state enable */ + stw r3, 0x54(r4) /* Boot enable, CS0 disable */ #endif /* CFG_LOWBOOT */ #if defined(CFG_DEFAULT_MBAR) && !defined(CFG_RAMBOOT) |