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author | Andrey Smirnov <andrew.smirnov@gmail.com> | 2017-06-19 07:40:37 -0700 |
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committer | Sascha Hauer <s.hauer@pengutronix.de> | 2017-06-21 08:33:28 +0200 |
commit | 5804dbe1599d8897d09703755b9bfa5bf779464a (patch) | |
tree | 1192632690b484db5a2db26a35ec2bb11d8917a0 /drivers/base | |
parent | a4c5612641338abba9ebf35f3655bcfff11cb05d (diff) | |
download | barebox-5804dbe1599d8897d09703755b9bfa5bf779464a.tar.gz barebox-5804dbe1599d8897d09703755b9bfa5bf779464a.tar.xz |
clk-vf610: Mark all of CCSR muxes with CLK_OPS_PARENT_ENABLE
As per VYBRIDRM.pdf, p. 673:
"... When switching clock sources on GL MUX, both active and target
clock sources must be active..."
So mark all of the clock muxes controlled by CCM_CSSR with
CLK_OPS_PARENT_ENABLE to satisfy that requirement. Experiment shows
that failing to do so would result in failure (in some cases CPU
hang).
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'drivers/base')
0 files changed, 0 insertions, 0 deletions