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| author | Ahmad Fatoum <a.fatoum@pengutronix.de> | 2023-11-27 07:49:38 +0100 |
|---|---|---|
| committer | Sascha Hauer <s.hauer@pengutronix.de> | 2023-12-05 08:45:32 +0100 |
| commit | 1484a59ee7feff318aca6e5ff294ac7ce9a86d7f (patch) | |
| tree | 4b365f297a1cbc41da9ffb3a166e6a8063e9cd94 /drivers/clk/clk-divider.c | |
| parent | 9853266ce27b7f2ea7722c17749aa17d01f4b4bd (diff) | |
| download | barebox-1484a59ee7feff318aca6e5ff294ac7ce9a86d7f.tar.gz barebox-1484a59ee7feff318aca6e5ff294ac7ce9a86d7f.tar.xz | |
clk: divider: implement CLK_DIVIDER_ALLOW_ZERO
We already support CLK_DIVIDER_ONE_BASED and incoming STM32MP13 clock
support can have clock dividers evaluate to zero. Add support for
CLK_DIVIDER_ALLOW_ZERO analogously to Linux.
Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Link: https://lore.barebox.org/20231127064947.2207726-5-a.fatoum@pengutronix.de
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'drivers/clk/clk-divider.c')
| -rw-r--r-- | drivers/clk/clk-divider.c | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/drivers/clk/clk-divider.c b/drivers/clk/clk-divider.c index 1eaff1675b..150b1fe60f 100644 --- a/drivers/clk/clk-divider.c +++ b/drivers/clk/clk-divider.c @@ -88,6 +88,12 @@ unsigned long divider_recalc_rate(struct clk *clk, unsigned long parent_rate, unsigned int div; div = _get_div(table, val, flags, width); + if (!div) { + WARN(!(flags & CLK_DIVIDER_ALLOW_ZERO), + "%s: Zero divisor and CLK_DIVIDER_ALLOW_ZERO not set\n", + clk->name); + return parent_rate; + } return DIV_ROUND_UP_ULL((u64)parent_rate, div); } |