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author | Sascha Hauer <s.hauer@pengutronix.de> | 2021-06-02 11:54:47 +0200 |
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committer | Sascha Hauer <s.hauer@pengutronix.de> | 2021-06-07 12:46:13 +0200 |
commit | 1e414657fca5afbc02b62068a9f456cf0907ce43 (patch) | |
tree | 2b11db45925930ce43075cd17330ee312d66a34b /drivers/clk/mxs/clk-ref.c | |
parent | f173bcb384dde795641a990dda55893ad78c4548 (diff) | |
download | barebox-1e414657fca5afbc02b62068a9f456cf0907ce43.tar.gz barebox-1e414657fca5afbc02b62068a9f456cf0907ce43.tar.xz |
clk: introduce struct clk_hw
In Linux the ops in struct clk_ops take a struct clk_hw * argument
instead of a struct clk * argument as in barebox. With this taking
new clk drivers from Linux requires a lot of mechanical conversions.
Instead of doing this over and over again swallow the pill once and
convert the existing barebox code over to clk_hw.
The implementation is a little different from Linux. In Linux struct clk
is only known to the core clock code. In barebox struct clk is
publically known and it is embedded into struct clk_hw. This allows
us to still use struct clk members in the clock drivers which we
currently still need, because otherwise this patch would be even
bigger.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Link: https://lore.barebox.org/20210602095507.24609-5-s.hauer@pengutronix.de
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'drivers/clk/mxs/clk-ref.c')
-rw-r--r-- | drivers/clk/mxs/clk-ref.c | 38 |
1 files changed, 19 insertions, 19 deletions
diff --git a/drivers/clk/mxs/clk-ref.c b/drivers/clk/mxs/clk-ref.c index 8c12e282ad..d483c9c6b2 100644 --- a/drivers/clk/mxs/clk-ref.c +++ b/drivers/clk/mxs/clk-ref.c @@ -23,20 +23,20 @@ * as pll rate * (18 / FRAC), where FRAC = 18 ~ 35. */ struct clk_ref { - struct clk clk; + struct clk_hw hw; const char *parent; void __iomem *reg; u8 idx; }; -#define to_clk_ref(_hw) container_of(_hw, struct clk_ref, clk) +#define to_clk_ref(_hw) container_of(_hw, struct clk_ref, hw) #define SET 0x4 #define CLR 0x8 -static int clk_ref_is_enabled(struct clk *clk) +static int clk_ref_is_enabled(struct clk_hw *hw) { - struct clk_ref *ref = to_clk_ref(clk); + struct clk_ref *ref = to_clk_ref(hw); u32 reg = readl(ref->reg); if (reg & 1 << ((ref->idx + 1) * 8 - 1)) @@ -45,26 +45,26 @@ static int clk_ref_is_enabled(struct clk *clk) return 1; } -static int clk_ref_enable(struct clk *clk) +static int clk_ref_enable(struct clk_hw *hw) { - struct clk_ref *ref = to_clk_ref(clk); + struct clk_ref *ref = to_clk_ref(hw); writel(1 << ((ref->idx + 1) * 8 - 1), ref->reg + CLR); return 0; } -static void clk_ref_disable(struct clk *clk) +static void clk_ref_disable(struct clk_hw *hw) { - struct clk_ref *ref = to_clk_ref(clk); + struct clk_ref *ref = to_clk_ref(hw); writel(1 << ((ref->idx + 1) * 8 - 1), ref->reg + SET); } -static unsigned long clk_ref_recalc_rate(struct clk *clk, +static unsigned long clk_ref_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) { - struct clk_ref *ref = to_clk_ref(clk); + struct clk_ref *ref = to_clk_ref(hw); u64 tmp = parent_rate; u8 frac = (readl(ref->reg) >> (ref->idx * 8)) & 0x3f; @@ -74,7 +74,7 @@ static unsigned long clk_ref_recalc_rate(struct clk *clk, return tmp; } -static long clk_ref_round_rate(struct clk *clk, unsigned long rate, +static long clk_ref_round_rate(struct clk_hw *hw, unsigned long rate, unsigned long *prate) { unsigned long parent_rate = *prate; @@ -97,10 +97,10 @@ static long clk_ref_round_rate(struct clk *clk, unsigned long rate, return tmp; } -static int clk_ref_set_rate(struct clk *clk, unsigned long rate, +static int clk_ref_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long parent_rate) { - struct clk_ref *ref = to_clk_ref(clk); + struct clk_ref *ref = to_clk_ref(hw); u64 tmp = parent_rate; u32 val; u32 frac, shift = ref->idx * 8; @@ -140,17 +140,17 @@ struct clk *mxs_clk_ref(const char *name, const char *parent_name, ref = xzalloc(sizeof(*ref)); ref->parent = parent_name; - ref->clk.name = name; - ref->clk.ops = &clk_ref_ops; - ref->clk.parent_names = &ref->parent; - ref->clk.num_parents = 1; + ref->hw.clk.name = name; + ref->hw.clk.ops = &clk_ref_ops; + ref->hw.clk.parent_names = &ref->parent; + ref->hw.clk.num_parents = 1; ref->reg = reg; ref->idx = idx; - ret = bclk_register(&ref->clk); + ret = bclk_register(&ref->hw.clk); if (ret) return ERR_PTR(ret); - return &ref->clk; + return &ref->hw.clk; } |