diff options
author | Sascha Hauer <s.hauer@pengutronix.de> | 2023-02-17 10:40:54 +0100 |
---|---|---|
committer | Sascha Hauer <s.hauer@pengutronix.de> | 2023-02-23 07:48:06 +0100 |
commit | 25e8115388be56fe23124562a5872b15dfecaa6e (patch) | |
tree | 303be41b9a88a3b1001a077d86b011940a212244 /drivers/clk | |
parent | 551aefef47622510d99b7c998f79ebf2d78389ef (diff) | |
download | barebox-25e8115388be56fe23124562a5872b15dfecaa6e.tar.gz barebox-25e8115388be56fe23124562a5872b15dfecaa6e.tar.xz |
clk: composite: Give mux/div/gate clks names
The mux/div/gate clks are never registered with the clk framework,
so names are normally not necessary. At least the mux clk might
end up in a call to clk_set_parent() though. This happens when a
mux shall change its rate and then reparents to the most suitable
parent. To get a better clue which being reparented there give the
mux a name and while at it give the other clocks names as well.
Link: https://lore.barebox.org/20230217094056.1894461-2-s.hauer@pengutronix.de
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'drivers/clk')
-rw-r--r-- | drivers/clk/rockchip/clk.c | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/drivers/clk/rockchip/clk.c b/drivers/clk/rockchip/clk.c index 6e7bba414f..5c074f526a 100644 --- a/drivers/clk/rockchip/clk.c +++ b/drivers/clk/rockchip/clk.c @@ -59,6 +59,7 @@ static struct clk *rockchip_clk_register_branch(const char *name, mux->width = mux_width; mux->flags = mux_flags; mux->lock = lock; + mux->hw.clk.name = basprintf("%s.mux", name); mux->hw.clk.ops = (mux_flags & CLK_MUX_READ_ONLY) ? &clk_mux_ro_ops : &clk_mux_ops; } @@ -74,6 +75,7 @@ static struct clk *rockchip_clk_register_branch(const char *name, gate->reg = base + gate_offset; gate->shift = gate_shift; gate->lock = lock; + gate->hw.clk.name = basprintf("%s.gate", name); gate->hw.clk.ops = &clk_gate_ops; } @@ -93,6 +95,7 @@ static struct clk *rockchip_clk_register_branch(const char *name, div->width = div_width; div->lock = lock; div->table = div_table; + div->hw.clk.name = basprintf("%s.div", name); div->hw.clk.ops = (div_flags & CLK_DIVIDER_READ_ONLY) ? &clk_divider_ro_ops : &clk_divider_ops; |