diff options
| author | Sascha Hauer <s.hauer@pengutronix.de> | 2018-11-09 10:55:04 +0100 |
|---|---|---|
| committer | Sascha Hauer <s.hauer@pengutronix.de> | 2018-11-09 10:55:04 +0100 |
| commit | 9a8f531efaa05ee2d1639bc7299a218f2f268612 (patch) | |
| tree | ae77602ffb081b0897ec934b912981009bccc478 /drivers/clk | |
| parent | b2cc1d18f57f8af42347a4b7a05afcc7e3e6d66d (diff) | |
| parent | bf36d5d6981012a44fdf38da1ec3a5966920c843 (diff) | |
| download | barebox-9a8f531efaa05ee2d1639bc7299a218f2f268612.tar.gz barebox-9a8f531efaa05ee2d1639bc7299a218f2f268612.tar.xz | |
Merge branch 'for-next/missing-prototypes'
Diffstat (limited to 'drivers/clk')
| -rw-r--r-- | drivers/clk/imx/clk-imx5.c | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/drivers/clk/imx/clk-imx5.c b/drivers/clk/imx/clk-imx5.c index edebd25a38..ae94e07f23 100644 --- a/drivers/clk/imx/clk-imx5.c +++ b/drivers/clk/imx/clk-imx5.c @@ -279,7 +279,7 @@ static void mx5_clocks_ipu_init(void __iomem *regs) clks[IMX5_CLK_IPU_SEL] = imx_clk_mux("ipu_sel", regs + CCM_CBCMR, 6, 2, ipu_sel, ARRAY_SIZE(ipu_sel)); } -int __init mx50_clocks_init(struct device_d *dev, void __iomem *regs) +static int __init mx50_clocks_init(struct device_d *dev, void __iomem *regs) { clks[IMX5_CLK_PLL1_SW] = imx_clk_pllv2("pll1_sw", "osc", (void *)MX50_PLL1_BASE_ADDR); @@ -366,7 +366,7 @@ static void mx51_clocks_ipu_init(void __iomem *regs) clkdev_add_physbase(clks[IMX5_CLK_IPU_DI1_SEL], MX51_IPU_BASE_ADDR, "di1"); } -int __init mx51_clocks_init(struct device_d *dev, void __iomem *regs) +static int __init mx51_clocks_init(struct device_d *dev, void __iomem *regs) { clks[IMX5_CLK_PLL1_SW] = imx_clk_pllv2("pll1_sw", "osc", (void *)MX51_PLL1_BASE_ADDR); clks[IMX5_CLK_PLL2_SW] = imx_clk_pllv2("pll2_sw", "osc", (void *)MX51_PLL2_BASE_ADDR); @@ -454,7 +454,7 @@ static void mx53_clocks_ipu_init(void __iomem *regs) clkdev_add_physbase(clks[IMX5_CLK_IPU_DI1_SEL], MX53_IPU_BASE_ADDR, "di1"); } -int __init mx53_clocks_init(struct device_d *dev, void __iomem *regs) +static int __init mx53_clocks_init(struct device_d *dev, void __iomem *regs) { clks[IMX5_CLK_PLL1_SW] = imx_clk_pllv2("pll1_sw", "osc", (void *)MX53_PLL1_BASE_ADDR); clks[IMX5_CLK_PLL2_SW] = imx_clk_pllv2("pll2_sw", "osc", (void *)MX53_PLL2_BASE_ADDR); |