diff options
| author | Alexander Shiyan <eagle.alexander923@gmail.com> | 2022-10-24 14:49:40 +0300 |
|---|---|---|
| committer | Sascha Hauer <s.hauer@pengutronix.de> | 2022-10-26 06:20:14 +0200 |
| commit | c2b65f066a6bf277203a8c5298e9c232ebf4d6f6 (patch) | |
| tree | dad5e41242aea1ff7aa532f08b9a4c0734406da9 /drivers/clk | |
| parent | 9f3477b0e9b3c0fec8afe196a1c0dcab7ad18b7c (diff) | |
| download | barebox-c2b65f066a6bf277203a8c5298e9c232ebf4d6f6.tar.gz barebox-c2b65f066a6bf277203a8c5298e9c232ebf4d6f6.tar.xz | |
clk: imx5: Add support for watchdog clock
This adds a dummy clock definition for i.MX-50/51/53 CPUs,
what makes the driver work.
Fixes: 87cad179648 ("watchdog: imxwd: get and enable clock")
Signed-off-by: Alexander Shiyan <eagle.alexander923@gmail.com>
Link: https://lore.barebox.org/20221024114940.26197-1-eagle.alexander923@gmail.com
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'drivers/clk')
| -rw-r--r-- | drivers/clk/imx/clk-imx5.c | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/drivers/clk/imx/clk-imx5.c b/drivers/clk/imx/clk-imx5.c index c7a1818bd7..81af9a9c88 100644 --- a/drivers/clk/imx/clk-imx5.c +++ b/drivers/clk/imx/clk-imx5.c @@ -205,6 +205,8 @@ static void __init mx5_clocks_common_init(struct device_d *dev, void __iomem *ba writel(0xffffffff, base + CCM_CCGR6); writel(0xffffffff, base + CCM_CCGR7); + clks[IMX5_CLK_DUMMY] = clk_fixed("dummy", 0); + if (!IS_ENABLED(CONFIG_COMMON_CLK_OF_PROVIDER) || !dev->device_node) { clks[IMX5_CLK_CKIL] = clk_fixed("ckil", 32768); clks[IMX5_CLK_OSC] = clk_fixed("osc", 24000000); @@ -312,6 +314,7 @@ static int __init mx50_clocks_init(struct device_d *dev, void __iomem *regs) clkdev_add_physbase(clks[IMX5_CLK_PER_ROOT], MX50_PWM1_BASE_ADDR, "per"); clkdev_add_physbase(clks[IMX5_CLK_PER_ROOT], MX50_PWM2_BASE_ADDR, "per"); clkdev_add_physbase(clks[IMX5_CLK_AHB], MX50_OTG_BASE_ADDR, NULL); + clkdev_add_physbase(clks[IMX5_CLK_DUMMY], MX50_WDOG1_BASE_ADDR, NULL); return 0; } @@ -392,6 +395,8 @@ static int __init mx51_clocks_init(struct device_d *dev, void __iomem *regs) clkdev_add_physbase(clks[IMX5_CLK_IPG], MX51_ATA_BASE_ADDR, NULL); clkdev_add_physbase(clks[IMX5_CLK_PER_ROOT], MX51_PWM1_BASE_ADDR, "per"); clkdev_add_physbase(clks[IMX5_CLK_PER_ROOT], MX51_PWM2_BASE_ADDR, "per"); + clkdev_add_physbase(clks[IMX5_CLK_DUMMY], MX51_WDOG_BASE_ADDR, NULL); + clkdev_add_physbase(clks[IMX5_CLK_DUMMY], MX51_WDOG2_BASE_ADDR, NULL); if (IS_ENABLED(CONFIG_DRIVER_VIDEO_IMX_IPUV3)) mx51_clocks_ipu_init(regs); @@ -488,6 +493,8 @@ static int __init mx53_clocks_init(struct device_d *dev, void __iomem *regs) clkdev_add_physbase(clks[IMX5_CLK_AHB], MX53_SATA_BASE_ADDR, NULL); clkdev_add_physbase(clks[IMX5_CLK_PER_ROOT], MX53_PWM1_BASE_ADDR, "per"); clkdev_add_physbase(clks[IMX5_CLK_PER_ROOT], MX53_PWM2_BASE_ADDR, "per"); + clkdev_add_physbase(clks[IMX5_CLK_DUMMY], MX53_WDOG1_BASE_ADDR, NULL); + clkdev_add_physbase(clks[IMX5_CLK_DUMMY], MX53_WDOG2_BASE_ADDR, NULL); if (IS_ENABLED(CONFIG_DRIVER_VIDEO_IMX_IPUV3)) mx53_clocks_ipu_init(regs); |