ddr: imx8m: move get_trained_CDD() to SoC code

get_trained_CDD() will be implemented differently on i.MX9, so move
the function to the i.MX8M specific file and add a hook to struct
dram_controller.

Link: https://lore.barebox.org/20231110130028.2123895-4-s.hauer@pengutronix.de
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

3 files changed, 172 insertions, 170 deletions

diff --git a/drivers/ddr/imx/ddrphy_train.c b/drivers/ddr/imx/ddrphy_train.c
index 1683ffd9a8..36fb6d3c11 100644
--- a/drivers/ddr/imx/ddrphy_train.c
+++ b/drivers/ddr/imx/ddrphy_train.c
@@ -159,7 +159,7 @@ int ddr_cfg_phy(struct dram_controller *dram, struct dram_timing_info *dram_timi
 		ddrphy_init_read_msg_block(fsp_msg->fw_type);
 
 		if (fsp_msg->fw_type != FW_2D_IMAGE)
-			get_trained_CDD(i);
+			dram->get_trained_CDD(dram, i);
 
 		dwc_ddrphy_apb_wr(0xd0000, 0x1);
 
diff --git a/drivers/ddr/imx/ddrphy_utils.c b/drivers/ddr/imx/ddrphy_utils.c
index 353a265136..db94b85b74 100644
--- a/drivers/ddr/imx/ddrphy_utils.c
+++ b/drivers/ddr/imx/ddrphy_utils.c
@@ -362,172 +362,3 @@ void ddrphy_init_set_dfi_clk(unsigned int drate_mhz, enum ddrc_type type)
 void ddrphy_init_read_msg_block(enum fw_type type)
 {
 }
-
-static unsigned int g_cdd_rr_max[4];
-static unsigned int g_cdd_rw_max[4];
-static unsigned int g_cdd_wr_max[4];
-static unsigned int g_cdd_ww_max[4];
-
-static unsigned int look_for_max(unsigned int data[], unsigned int addr_start,
-				 unsigned int addr_end)
-{
-	unsigned int i, imax = 0;
-
-	for (i = addr_start; i <= addr_end; i++) {
-		if (((data[i] >> 7) == 0) && (data[i] > imax))
-			imax = data[i];
-	}
-
-	return imax;
-}
-
-void get_trained_CDD(u32 fsp)
-{
-	unsigned int i, ddr_type, tmp;
-	unsigned int cdd_cha[12], cdd_chb[12];
-	unsigned int cdd_cha_rr_max, cdd_cha_rw_max, cdd_cha_wr_max, cdd_cha_ww_max;
-	unsigned int cdd_chb_rr_max, cdd_chb_rw_max, cdd_chb_wr_max, cdd_chb_ww_max;
-
-	ddr_type = reg32_read(DDRC_MSTR(0)) & 0x3f;
-	if (ddr_type == 0x20) {
-		for (i = 0; i < 6; i++) {
-			tmp = reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0) +
-					 (0x54013UL + i) * 4);
-			cdd_cha[i * 2] = tmp & 0xff;
-			cdd_cha[i * 2 + 1] = (tmp >> 8) & 0xff;
-		}
-
-		for (i = 0; i < 7; i++) {
-			tmp = reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0) +
-					 (0x5402cUL + i) * 4);
-			if (i == 0) {
-				cdd_cha[0] = (tmp >> 8) & 0xff;
-			} else if (i == 6) {
-				cdd_cha[11] = tmp & 0xff;
-			} else {
-				cdd_chb[ i * 2 - 1] = tmp & 0xff;
-				cdd_chb[i * 2] = (tmp >> 8) & 0xff;
-			}
-		}
-
-		cdd_cha_rr_max = look_for_max(cdd_cha, 0, 1);
-		cdd_cha_rw_max = look_for_max(cdd_cha, 2, 5);
-		cdd_cha_wr_max = look_for_max(cdd_cha, 6, 9);
-		cdd_cha_ww_max = look_for_max(cdd_cha, 10, 11);
-		cdd_chb_rr_max = look_for_max(cdd_chb, 0, 1);
-		cdd_chb_rw_max = look_for_max(cdd_chb, 2, 5);
-		cdd_chb_wr_max = look_for_max(cdd_chb, 6, 9);
-		cdd_chb_ww_max = look_for_max(cdd_chb, 10, 11);
-		g_cdd_rr_max[fsp] =  cdd_cha_rr_max > cdd_chb_rr_max ? cdd_cha_rr_max : cdd_chb_rr_max;
-		g_cdd_rw_max[fsp] =  cdd_cha_rw_max > cdd_chb_rw_max ? cdd_cha_rw_max : cdd_chb_rw_max;
-		g_cdd_wr_max[fsp] =  cdd_cha_wr_max > cdd_chb_wr_max ? cdd_cha_wr_max : cdd_chb_wr_max;
-		g_cdd_ww_max[fsp] =  cdd_cha_ww_max > cdd_chb_ww_max ? cdd_cha_ww_max : cdd_chb_ww_max;
-	} else {
-		unsigned int ddr4_cdd[64];
-
-		for( i = 0; i < 29; i++) {
-			tmp = reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0) +
-					 (0x54012UL + i) * 4);
-			ddr4_cdd[i * 2] = tmp & 0xff;
-			ddr4_cdd[i * 2 + 1] = (tmp >> 8) & 0xff;
-		}
-
-		g_cdd_rr_max[fsp] = look_for_max(ddr4_cdd, 1, 12);
-		g_cdd_ww_max[fsp] = look_for_max(ddr4_cdd, 13, 24);
-		g_cdd_rw_max[fsp] = look_for_max(ddr4_cdd, 25, 40);
-		g_cdd_wr_max[fsp] = look_for_max(ddr4_cdd, 41, 56);
-	}
-}
-
-void update_umctl2_rank_space_setting(unsigned int pstat_num,
-				      enum ddrc_type type)
-{
-	unsigned int i,ddr_type;
-	unsigned int rdata, tmp, tmp_t;
-	unsigned int ddrc_w2r,ddrc_r2w,ddrc_wr_gap,ddrc_rd_gap;
-	unsigned long addr_slot;
-
-	ddr_type = reg32_read(DDRC_MSTR(0)) & 0x3f;
-	for (i = 0; i < pstat_num; i++) {
-		addr_slot = i ? (i + 1) * 0x1000 : 0;
-		if (ddr_type == 0x20) {
-			/* update r2w:[13:8], w2r:[5:0] */
-			rdata = reg32_read(DDRC_DRAMTMG2(0) + addr_slot);
-			ddrc_w2r = rdata & 0x3f;
-			if (type == DDRC_TYPE_MP)
-				tmp = ddrc_w2r + (g_cdd_wr_max[i] >> 1);
-			else
-				tmp = ddrc_w2r + (g_cdd_wr_max[i] >> 1) + 1;
-			ddrc_w2r = (tmp > 0x3f) ? 0x3f : tmp;
-
-			ddrc_r2w = (rdata >> 8) & 0x3f;
-			if (type == DDRC_TYPE_MP)
-				tmp = ddrc_r2w + (g_cdd_rw_max[i] >> 1);
-			else
-				tmp = ddrc_r2w + (g_cdd_rw_max[i] >> 1) + 1;
-			ddrc_r2w = (tmp > 0x3f) ? 0x3f : tmp;
-
-			tmp_t = (rdata & 0xffffc0c0) | (ddrc_r2w << 8) | ddrc_w2r;
-			reg32_write((DDRC_DRAMTMG2(0) + addr_slot), tmp_t);
-		} else {
-			/* update w2r:[5:0] */
-			rdata = reg32_read(DDRC_DRAMTMG9(0) + addr_slot);
-			ddrc_w2r = rdata & 0x3f;
-			if (type == DDRC_TYPE_MP)
-				tmp = ddrc_w2r + (g_cdd_wr_max[i] >> 1);
-			else
-				tmp = ddrc_w2r + (g_cdd_wr_max[i] >> 1) + 1;
-			ddrc_w2r = (tmp > 0x3f) ? 0x3f : tmp;
-			tmp_t = (rdata & 0xffffffc0) | ddrc_w2r;
-			reg32_write((DDRC_DRAMTMG9(0) + addr_slot), tmp_t);
-
-			/* update r2w:[13:8] */
-			rdata = reg32_read(DDRC_DRAMTMG2(0) + addr_slot);
-			ddrc_r2w = (rdata >> 8) & 0x3f;
-			if (type == DDRC_TYPE_MP)
-				tmp = ddrc_r2w + (g_cdd_rw_max[i] >> 1);
-			else
-				tmp = ddrc_r2w + (g_cdd_rw_max[i] >> 1) + 1;
-			ddrc_r2w = (tmp > 0x3f) ? 0x3f : tmp;
-
-			tmp_t = (rdata & 0xffffc0ff) | (ddrc_r2w << 8);
-			reg32_write((DDRC_DRAMTMG2(0) + addr_slot), tmp_t);
-		}
-
-		if (type != DDRC_TYPE_MQ) {
-			/* update rankctl: wr_gap:11:8; rd:gap:7:4; quasi-dymic, doc wrong(static) */
-			rdata = reg32_read(DDRC_RANKCTL(0) + addr_slot);
-			ddrc_wr_gap = (rdata >> 8) & 0xf;
-			if (type == DDRC_TYPE_MP)
-				tmp = ddrc_wr_gap + (g_cdd_ww_max[i] >> 1);
-			else
-				tmp = ddrc_wr_gap + (g_cdd_ww_max[i] >> 1) + 1;
-			ddrc_wr_gap = (tmp > 0xf) ? 0xf : tmp;
-
-			ddrc_rd_gap = (rdata >> 4) & 0xf;
-			if (type == DDRC_TYPE_MP)
-				tmp = ddrc_rd_gap + (g_cdd_rr_max[i] >> 1);
-			else
-				tmp = ddrc_rd_gap + (g_cdd_rr_max[i] >> 1) + 1;
-			ddrc_rd_gap = (tmp > 0xf) ? 0xf : tmp;
-
-			tmp_t = (rdata & 0xfffff00f) | (ddrc_wr_gap << 8) | (ddrc_rd_gap << 4);
-			reg32_write((DDRC_RANKCTL(0) + addr_slot), tmp_t);
-		}
-	}
-
-	if (type == DDRC_TYPE_MQ) {
-		/* update rankctl: wr_gap:11:8; rd:gap:7:4; quasi-dymic, doc wrong(static) */
-		rdata = reg32_read(DDRC_RANKCTL(0));
-		ddrc_wr_gap = (rdata >> 8) & 0xf;
-		tmp = ddrc_wr_gap + (g_cdd_ww_max[0] >> 1) + 1;
-		ddrc_wr_gap = (tmp > 0xf) ? 0xf : tmp;
-
-		ddrc_rd_gap = (rdata >> 4) & 0xf;
-		tmp = ddrc_rd_gap + (g_cdd_rr_max[0] >> 1) + 1;
-		ddrc_rd_gap = (tmp > 0xf) ? 0xf : tmp;
-
-		tmp_t = (rdata & 0xfffff00f) | (ddrc_wr_gap << 8) | (ddrc_rd_gap << 4);
-		reg32_write(DDRC_RANKCTL(0), tmp_t);
-	}
-}
diff --git a/drivers/ddr/imx/imx8m_ddr_init.c b/drivers/ddr/imx/imx8m_ddr_init.c
index 8acacfac35..1e704ef8fc 100644
--- a/drivers/ddr/imx/imx8m_ddr_init.c
+++ b/drivers/ddr/imx/imx8m_ddr_init.c
@@ -43,6 +43,175 @@ static void ddr_cfg_umctl2(struct dram_cfg_param *ddrc_cfg, int num)
 	}
 }
 
+static unsigned int g_cdd_rr_max[4];
+static unsigned int g_cdd_rw_max[4];
+static unsigned int g_cdd_wr_max[4];
+static unsigned int g_cdd_ww_max[4];
+
+static unsigned int look_for_max(unsigned int data[], unsigned int addr_start,
+				 unsigned int addr_end)
+{
+	unsigned int i, imax = 0;
+
+	for (i = addr_start; i <= addr_end; i++) {
+		if (((data[i] >> 7) == 0) && (data[i] > imax))
+			imax = data[i];
+	}
+
+	return imax;
+}
+
+static void get_trained_CDD(struct dram_controller *dram, u32 fsp)
+{
+	unsigned int i, ddr_type, tmp;
+	unsigned int cdd_cha[12], cdd_chb[12];
+	unsigned int cdd_cha_rr_max, cdd_cha_rw_max, cdd_cha_wr_max, cdd_cha_ww_max;
+	unsigned int cdd_chb_rr_max, cdd_chb_rw_max, cdd_chb_wr_max, cdd_chb_ww_max;
+
+	ddr_type = reg32_read(DDRC_MSTR(0)) & 0x3f;
+	if (ddr_type == 0x20) {
+		for (i = 0; i < 6; i++) {
+			tmp = reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0) +
+					 (0x54013UL + i) * 4);
+			cdd_cha[i * 2] = tmp & 0xff;
+			cdd_cha[i * 2 + 1] = (tmp >> 8) & 0xff;
+		}
+
+		for (i = 0; i < 7; i++) {
+			tmp = reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0) +
+					 (0x5402cUL + i) * 4);
+			if (i == 0) {
+				cdd_cha[0] = (tmp >> 8) & 0xff;
+			} else if (i == 6) {
+				cdd_cha[11] = tmp & 0xff;
+			} else {
+				cdd_chb[ i * 2 - 1] = tmp & 0xff;
+				cdd_chb[i * 2] = (tmp >> 8) & 0xff;
+			}
+		}
+
+		cdd_cha_rr_max = look_for_max(cdd_cha, 0, 1);
+		cdd_cha_rw_max = look_for_max(cdd_cha, 2, 5);
+		cdd_cha_wr_max = look_for_max(cdd_cha, 6, 9);
+		cdd_cha_ww_max = look_for_max(cdd_cha, 10, 11);
+		cdd_chb_rr_max = look_for_max(cdd_chb, 0, 1);
+		cdd_chb_rw_max = look_for_max(cdd_chb, 2, 5);
+		cdd_chb_wr_max = look_for_max(cdd_chb, 6, 9);
+		cdd_chb_ww_max = look_for_max(cdd_chb, 10, 11);
+		g_cdd_rr_max[fsp] =  cdd_cha_rr_max > cdd_chb_rr_max ? cdd_cha_rr_max : cdd_chb_rr_max;
+		g_cdd_rw_max[fsp] =  cdd_cha_rw_max > cdd_chb_rw_max ? cdd_cha_rw_max : cdd_chb_rw_max;
+		g_cdd_wr_max[fsp] =  cdd_cha_wr_max > cdd_chb_wr_max ? cdd_cha_wr_max : cdd_chb_wr_max;
+		g_cdd_ww_max[fsp] =  cdd_cha_ww_max > cdd_chb_ww_max ? cdd_cha_ww_max : cdd_chb_ww_max;
+	} else {
+		unsigned int ddr4_cdd[64];
+
+		for( i = 0; i < 29; i++) {
+			tmp = reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0) +
+					 (0x54012UL + i) * 4);
+			ddr4_cdd[i * 2] = tmp & 0xff;
+			ddr4_cdd[i * 2 + 1] = (tmp >> 8) & 0xff;
+		}
+
+		g_cdd_rr_max[fsp] = look_for_max(ddr4_cdd, 1, 12);
+		g_cdd_ww_max[fsp] = look_for_max(ddr4_cdd, 13, 24);
+		g_cdd_rw_max[fsp] = look_for_max(ddr4_cdd, 25, 40);
+		g_cdd_wr_max[fsp] = look_for_max(ddr4_cdd, 41, 56);
+	}
+}
+
+static void update_umctl2_rank_space_setting(unsigned int pstat_num,
+					     enum ddrc_type type)
+{
+	unsigned int i,ddr_type;
+	unsigned int rdata, tmp, tmp_t;
+	unsigned int ddrc_w2r,ddrc_r2w,ddrc_wr_gap,ddrc_rd_gap;
+	unsigned long addr_slot;
+
+	ddr_type = reg32_read(DDRC_MSTR(0)) & 0x3f;
+	for (i = 0; i < pstat_num; i++) {
+		addr_slot = i ? (i + 1) * 0x1000 : 0;
+		if (ddr_type == 0x20) {
+			/* update r2w:[13:8], w2r:[5:0] */
+			rdata = reg32_read(DDRC_DRAMTMG2(0) + addr_slot);
+			ddrc_w2r = rdata & 0x3f;
+			if (type == DDRC_TYPE_MP)
+				tmp = ddrc_w2r + (g_cdd_wr_max[i] >> 1);
+			else
+				tmp = ddrc_w2r + (g_cdd_wr_max[i] >> 1) + 1;
+			ddrc_w2r = (tmp > 0x3f) ? 0x3f : tmp;
+
+			ddrc_r2w = (rdata >> 8) & 0x3f;
+			if (type == DDRC_TYPE_MP)
+				tmp = ddrc_r2w + (g_cdd_rw_max[i] >> 1);
+			else
+				tmp = ddrc_r2w + (g_cdd_rw_max[i] >> 1) + 1;
+			ddrc_r2w = (tmp > 0x3f) ? 0x3f : tmp;
+
+			tmp_t = (rdata & 0xffffc0c0) | (ddrc_r2w << 8) | ddrc_w2r;
+			reg32_write((DDRC_DRAMTMG2(0) + addr_slot), tmp_t);
+		} else {
+			/* update w2r:[5:0] */
+			rdata = reg32_read(DDRC_DRAMTMG9(0) + addr_slot);
+			ddrc_w2r = rdata & 0x3f;
+			if (type == DDRC_TYPE_MP)
+				tmp = ddrc_w2r + (g_cdd_wr_max[i] >> 1);
+			else
+				tmp = ddrc_w2r + (g_cdd_wr_max[i] >> 1) + 1;
+			ddrc_w2r = (tmp > 0x3f) ? 0x3f : tmp;
+			tmp_t = (rdata & 0xffffffc0) | ddrc_w2r;
+			reg32_write((DDRC_DRAMTMG9(0) + addr_slot), tmp_t);
+
+			/* update r2w:[13:8] */
+			rdata = reg32_read(DDRC_DRAMTMG2(0) + addr_slot);
+			ddrc_r2w = (rdata >> 8) & 0x3f;
+			if (type == DDRC_TYPE_MP)
+				tmp = ddrc_r2w + (g_cdd_rw_max[i] >> 1);
+			else
+				tmp = ddrc_r2w + (g_cdd_rw_max[i] >> 1) + 1;
+			ddrc_r2w = (tmp > 0x3f) ? 0x3f : tmp;
+
+			tmp_t = (rdata & 0xffffc0ff) | (ddrc_r2w << 8);
+			reg32_write((DDRC_DRAMTMG2(0) + addr_slot), tmp_t);
+		}
+
+		if (type != DDRC_TYPE_MQ) {
+			/* update rankctl: wr_gap:11:8; rd:gap:7:4; quasi-dymic, doc wrong(static) */
+			rdata = reg32_read(DDRC_RANKCTL(0) + addr_slot);
+			ddrc_wr_gap = (rdata >> 8) & 0xf;
+			if (type == DDRC_TYPE_MP)
+				tmp = ddrc_wr_gap + (g_cdd_ww_max[i] >> 1);
+			else
+				tmp = ddrc_wr_gap + (g_cdd_ww_max[i] >> 1) + 1;
+			ddrc_wr_gap = (tmp > 0xf) ? 0xf : tmp;
+
+			ddrc_rd_gap = (rdata >> 4) & 0xf;
+			if (type == DDRC_TYPE_MP)
+				tmp = ddrc_rd_gap + (g_cdd_rr_max[i] >> 1);
+			else
+				tmp = ddrc_rd_gap + (g_cdd_rr_max[i] >> 1) + 1;
+			ddrc_rd_gap = (tmp > 0xf) ? 0xf : tmp;
+
+			tmp_t = (rdata & 0xfffff00f) | (ddrc_wr_gap << 8) | (ddrc_rd_gap << 4);
+			reg32_write((DDRC_RANKCTL(0) + addr_slot), tmp_t);
+		}
+	}
+
+	if (type == DDRC_TYPE_MQ) {
+		/* update rankctl: wr_gap:11:8; rd:gap:7:4; quasi-dymic, doc wrong(static) */
+		rdata = reg32_read(DDRC_RANKCTL(0));
+		ddrc_wr_gap = (rdata >> 8) & 0xf;
+		tmp = ddrc_wr_gap + (g_cdd_ww_max[0] >> 1) + 1;
+		ddrc_wr_gap = (tmp > 0xf) ? 0xf : tmp;
+
+		ddrc_rd_gap = (rdata >> 4) & 0xf;
+		tmp = ddrc_rd_gap + (g_cdd_rr_max[0] >> 1) + 1;
+		ddrc_rd_gap = (tmp > 0xf) ? 0xf : tmp;
+
+		tmp_t = (rdata & 0xfffff00f) | (ddrc_wr_gap << 8) | (ddrc_rd_gap << 4);
+		reg32_write(DDRC_RANKCTL(0), tmp_t);
+	}
+}
+
 /*
  * We store the timing parameters here. the TF-A will pick these up.
  * Note that the timing used we leave the driver with is a PLL bypass 25MHz
@@ -59,6 +228,8 @@ int imx8m_ddr_init(struct dram_controller *dram, struct dram_timing_info *dram_t
 
 	pr_debug("start DRAM init\n");
 
+	dram->get_trained_CDD = get_trained_CDD;
+
 	/* Step1: Follow the power up procedure */
 	switch (dram->ddrc_type) {
 	case DDRC_TYPE_MQ: