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| author | Sascha Hauer <s.hauer@pengutronix.de> | 2023-11-10 14:00:20 +0100 |
|---|---|---|
| committer | Sascha Hauer <s.hauer@pengutronix.de> | 2023-11-13 13:48:03 +0100 |
| commit | 215d6a6722d4edd8e451e37ccb970b297dc319b2 (patch) | |
| tree | 92af7ecb51f2210a3fe73f7eff0e41a973ed6fc4 /drivers/ddr | |
| parent | f8d836f57cc81a43aead76b15c59cd54eabf1d1d (diff) | |
| download | barebox-215d6a6722d4edd8e451e37ccb970b297dc319b2.tar.gz barebox-215d6a6722d4edd8e451e37ccb970b297dc319b2.tar.xz | |
ddr: imx8m: clean up defines
Use register defines we already have in mach/imx/imx8m-regs.h rather
than duplicating them in the ddr code. Also remove some unused defines.
Link: https://lore.barebox.org/20231110130028.2123895-6-s.hauer@pengutronix.de
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'drivers/ddr')
| -rw-r--r-- | drivers/ddr/imx/helper.c | 8 | ||||
| -rw-r--r-- | drivers/ddr/imx/imx8m_ddr_init.c | 2 |
2 files changed, 1 insertions, 9 deletions
diff --git a/drivers/ddr/imx/helper.c b/drivers/ddr/imx/helper.c index 98e4084958..81c3ed7f30 100644 --- a/drivers/ddr/imx/helper.c +++ b/drivers/ddr/imx/helper.c @@ -10,14 +10,6 @@ #include <errno.h> #include <soc/imx8m/ddr.h> -#define IMEM_LEN 32768 /* byte */ -#define DMEM_LEN 16384 /* byte */ -#define IMEM_2D_OFFSET 49152 - -#define IMEM_OFFSET_ADDR 0x00050000 -#define DMEM_OFFSET_ADDR 0x00054000 -#define DDR_TRAIN_CODE_BASE_ADDR IP2APB_DDRPHY_IPS_BASE_ADDR(0) - void ddrphy_trained_csr_save(struct dram_cfg_param *ddrphy_csr, unsigned int num) { diff --git a/drivers/ddr/imx/imx8m_ddr_init.c b/drivers/ddr/imx/imx8m_ddr_init.c index 856e7ee4fe..f76aafe769 100644 --- a/drivers/ddr/imx/imx8m_ddr_init.c +++ b/drivers/ddr/imx/imx8m_ddr_init.c @@ -543,7 +543,7 @@ int imx8m_ddr_init(struct dram_controller *dram, struct dram_timing_info *dram_t */ tmp = reg32_read(DDRC_MSTR(0)); if (tmp & (0x1 << 5) && dram->ddrc_type != DDRC_TYPE_MN) - reg32_write(DDRC_DDR_SS_GPR0, 0x01); /* LPDDR4 mode */ + reg32_write(MX8M_DDRC_DDR_SS_GPR0, 0x01); /* LPDDR4 mode */ /* determine the initial boot frequency */ target_freq = reg32_read(DDRC_MSTR2(0)) & 0x3; |