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authorAhmad Fatoum <a.fatoum@pengutronix.de>2021-10-01 12:09:46 +0200
committerSascha Hauer <s.hauer@pengutronix.de>2021-10-05 09:05:37 +0200
commit36b5417fe6f0fce432fb219edef996891336179c (patch)
tree4a7453e1fa59d56e30d2a8003aa828df5dba950b /drivers/ddr
parent652b97780fbd05458e478b9f37471dd774b6b210 (diff)
downloadbarebox-36b5417fe6f0fce432fb219edef996891336179c.tar.gz
barebox-36b5417fe6f0fce432fb219edef996891336179c.tar.xz
ddr: imx8m: add i.MX8MN (Nano) support
DRAM setup on i.MX8MP is the same as on the i.MX8MP, except for DDRC_DDR_SS_GPR0, which the vendor's U-Boot port explicitly skips on the nano, irrespective of the configured DRAM type. Do likewise. Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Link: https://lore.barebox.org/20211001100949.6891-6-a.fatoum@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'drivers/ddr')
-rw-r--r--drivers/ddr/imx8m/Kconfig2
-rw-r--r--drivers/ddr/imx8m/ddr_init.c8
-rw-r--r--drivers/ddr/imx8m/ddrphy_utils.c1
3 files changed, 9 insertions, 2 deletions
diff --git a/drivers/ddr/imx8m/Kconfig b/drivers/ddr/imx8m/Kconfig
index 7673ab5b4c..efc50c21d4 100644
--- a/drivers/ddr/imx8m/Kconfig
+++ b/drivers/ddr/imx8m/Kconfig
@@ -1,5 +1,5 @@
menu "i.MX8M DDR controllers"
- depends on ARCH_IMX8MQ || ARCH_IMX8MM || ARCH_IMX8MP
+ depends on ARCH_IMX8MQ || ARCH_IMX8MM || ARCH_IMX8MN || ARCH_IMX8MP
config IMX8M_DRAM
bool "imx8m dram controller support"
diff --git a/drivers/ddr/imx8m/ddr_init.c b/drivers/ddr/imx8m/ddr_init.c
index 34da44af64..95ac76efcd 100644
--- a/drivers/ddr/imx8m/ddr_init.c
+++ b/drivers/ddr/imx8m/ddr_init.c
@@ -48,6 +48,7 @@ static int imx8m_ddr_init(struct dram_timing_info *dram_timing,
reg32_write(src_ddrc_rcr + 0x04, 0x8f000000);
break;
case DDRC_TYPE_MM:
+ case DDRC_TYPE_MN:
case DDRC_TYPE_MP:
reg32_write(src_ddrc_rcr, 0x8f00001f);
reg32_write(src_ddrc_rcr, 0x8f00000f);
@@ -88,7 +89,7 @@ static int imx8m_ddr_init(struct dram_timing_info *dram_timing,
/* if ddr type is LPDDR4, do it */
tmp = reg32_read(DDRC_MSTR(0));
- if (tmp & (0x1 << 5))
+ if (tmp & (0x1 << 5) && type != DDRC_TYPE_MN)
reg32_write(DDRC_DDR_SS_GPR0, 0x01); /* LPDDR4 mode */
/* determine the initial boot frequency */
@@ -197,6 +198,11 @@ int imx8mm_ddr_init(struct dram_timing_info *dram_timing)
return imx8m_ddr_init(dram_timing, DDRC_TYPE_MM);
}
+int imx8mn_ddr_init(struct dram_timing_info *dram_timing)
+{
+ return imx8m_ddr_init(dram_timing, DDRC_TYPE_MN);
+}
+
int imx8mq_ddr_init(struct dram_timing_info *dram_timing)
{
return imx8m_ddr_init(dram_timing, DDRC_TYPE_MQ);
diff --git a/drivers/ddr/imx8m/ddrphy_utils.c b/drivers/ddr/imx8m/ddrphy_utils.c
index a56033f780..79bb76c35a 100644
--- a/drivers/ddr/imx8m/ddrphy_utils.c
+++ b/drivers/ddr/imx8m/ddrphy_utils.c
@@ -321,6 +321,7 @@ static int dram_pll_init(enum ddr_rate drate, enum ddrc_type type)
case DDRC_TYPE_MQ:
return dram_sscg_pll_init(drate);
case DDRC_TYPE_MM:
+ case DDRC_TYPE_MN:
case DDRC_TYPE_MP:
return dram_frac_pll_init(drate);
default: