diff options
| author | Ahmad Fatoum <a.fatoum@pengutronix.de> | 2022-08-05 14:54:09 +0200 |
|---|---|---|
| committer | Sascha Hauer <s.hauer@pengutronix.de> | 2022-08-08 14:32:08 +0200 |
| commit | 6e48ef8732de8bd6fc8df69a5c87100ebf3ba8d1 (patch) | |
| tree | a5514892c424e42fa7e4e9764a3787c54261129f /drivers/ddr | |
| parent | e90542e1eaed2f16c2f85b7d6b26db6b74476609 (diff) | |
| download | barebox-6e48ef8732de8bd6fc8df69a5c87100ebf3ba8d1.tar.gz barebox-6e48ef8732de8bd6fc8df69a5c87100ebf3ba8d1.tar.xz | |
ddr: imx8m: rename type to more fitting ddrc|dram_type
type is ambiguous and can mean either DDR controller (SoC) type, DRAM
type or firmware (1D/2D) type. Replace variables called type plainly,
with more descriptive ddrc_type, dram_type and fw_type.
Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Reviewed-by: Marco Felsch <m.felsch@pengutronix.de>
Link: https://lore.barebox.org/20220805125413.1046239-6-a.fatoum@pengutronix.de
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'drivers/ddr')
| -rw-r--r-- | drivers/ddr/imx8m/ddr_init.c | 12 | ||||
| -rw-r--r-- | drivers/ddr/imx8m/ddrphy_train.c | 4 |
2 files changed, 8 insertions, 8 deletions
diff --git a/drivers/ddr/imx8m/ddr_init.c b/drivers/ddr/imx8m/ddr_init.c index 41e1fba38a..f046ea52df 100644 --- a/drivers/ddr/imx8m/ddr_init.c +++ b/drivers/ddr/imx8m/ddr_init.c @@ -50,7 +50,7 @@ static void ddr_cfg_umctl2(struct dram_cfg_param *ddrc_cfg, int num) #define IMX8M_SAVED_DRAM_TIMING_BASE 0x180000 int imx8m_ddr_init(struct dram_timing_info *dram_timing, - enum ddrc_type type) + enum ddrc_type ddrc_type) { unsigned long src_ddrc_rcr = MX8M_SRC_DDRC_RCR_ADDR; unsigned int tmp, initial_drate, target_freq; @@ -59,7 +59,7 @@ int imx8m_ddr_init(struct dram_timing_info *dram_timing, pr_debug("start DRAM init\n"); /* Step1: Follow the power up procedure */ - switch (type) { + switch (ddrc_type) { case DDRC_TYPE_MQ: reg32_write(src_ddrc_rcr + 0x04, 0x8f00000f); reg32_write(src_ddrc_rcr, 0x8f00000f); @@ -81,7 +81,7 @@ int imx8m_ddr_init(struct dram_timing_info *dram_timing, initial_drate = dram_timing->fsp_msg[0].drate; /* default to the frequency point 0 clock */ - ddrphy_init_set_dfi_clk(initial_drate, type); + ddrphy_init_set_dfi_clk(initial_drate, ddrc_type); /* D-aasert the presetn */ reg32_write(src_ddrc_rcr, 0x8F000006); @@ -107,7 +107,7 @@ int imx8m_ddr_init(struct dram_timing_info *dram_timing, /* if ddr type is LPDDR4, do it */ tmp = reg32_read(DDRC_MSTR(0)); - if (tmp & (0x1 << 5) && type != DDRC_TYPE_MN) + if (tmp & (0x1 << 5) && ddrc_type != DDRC_TYPE_MN) reg32_write(DDRC_DDR_SS_GPR0, 0x01); /* LPDDR4 mode */ /* determine the initial boot frequency */ @@ -134,7 +134,7 @@ int imx8m_ddr_init(struct dram_timing_info *dram_timing, */ pr_debug("ddrphy config start\n"); - ret = ddr_cfg_phy(dram_timing, type); + ret = ddr_cfg_phy(dram_timing, ddrc_type); if (ret) return ret; @@ -154,7 +154,7 @@ int imx8m_ddr_init(struct dram_timing_info *dram_timing, reg32_write(DDRC_SWCTL(0), 0x00000000); /* Apply rank-to-rank workaround */ - update_umctl2_rank_space_setting(dram_timing->fsp_msg_num - 1, type); + update_umctl2_rank_space_setting(dram_timing->fsp_msg_num - 1, ddrc_type); /* Step16: Set DFIMISC.dfi_init_start to 1 */ setbits_le32(DDRC_DFIMISC(0), (0x1 << 5)); diff --git a/drivers/ddr/imx8m/ddrphy_train.c b/drivers/ddr/imx8m/ddrphy_train.c index 2190b53413..f739c65107 100644 --- a/drivers/ddr/imx8m/ddrphy_train.c +++ b/drivers/ddr/imx8m/ddrphy_train.c @@ -93,7 +93,7 @@ void ddr_load_train_code(enum dram_type dram_type, enum fw_type fw_type) DDRC_PHY_DMEM, dmem, dsize); } -int ddr_cfg_phy(struct dram_timing_info *dram_timing, enum ddrc_type type) +int ddr_cfg_phy(struct dram_timing_info *dram_timing, enum ddrc_type ddrc_type) { struct dram_cfg_param *dram_cfg; struct dram_fsp_msg *fsp_msg; @@ -116,7 +116,7 @@ int ddr_cfg_phy(struct dram_timing_info *dram_timing, enum ddrc_type type) for (i = 0; i < dram_timing->fsp_msg_num; i++) { pr_debug("DRAM PHY training for %dMTS\n", fsp_msg->drate); /* set dram PHY input clocks to desired frequency */ - ddrphy_init_set_dfi_clk(fsp_msg->drate, type); + ddrphy_init_set_dfi_clk(fsp_msg->drate, ddrc_type); /* load the dram training firmware image */ dwc_ddrphy_apb_wr(0xd0000, 0x0); |