diff options
| author | Sascha Hauer <s.hauer@pengutronix.de> | 2023-12-19 14:18:02 +0100 |
|---|---|---|
| committer | Sascha Hauer <s.hauer@pengutronix.de> | 2024-01-02 12:36:36 +0100 |
| commit | 916d550480d065e91ae30924c12ca0d97d88f7db (patch) | |
| tree | 9a255b295621bc40fe62e1f53c79f13e37161600 /drivers/ddr | |
| parent | ed9e0d1db50ebe0d4f410ad892cce7a51474740a (diff) | |
| download | barebox-916d550480d065e91ae30924c12ca0d97d88f7db.tar.gz barebox-916d550480d065e91ae30924c12ca0d97d88f7db.tar.xz | |
fsl-ddr: make endianess runtime decision
Link: https://lore.barebox.org/20231219131802.7475-3-s.hauer@pengutronix.de
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'drivers/ddr')
| -rw-r--r-- | drivers/ddr/fsl/arm_ddr_gen3.c | 7 | ||||
| -rw-r--r-- | drivers/ddr/fsl/fsl_ddr_gen4.c | 7 | ||||
| -rw-r--r-- | drivers/ddr/fsl/main.c | 13 |
3 files changed, 22 insertions, 5 deletions
diff --git a/drivers/ddr/fsl/arm_ddr_gen3.c b/drivers/ddr/fsl/arm_ddr_gen3.c index a8b96f1261..1cbdb1446f 100644 --- a/drivers/ddr/fsl/arm_ddr_gen3.c +++ b/drivers/ddr/fsl/arm_ddr_gen3.c @@ -21,7 +21,7 @@ * Dividing the initialization to two steps to deassert DDR reset signal * to comply with JEDEC specs for RDIMMs. */ -void fsl_ddr_set_memctl_regs(struct fsl_ddr_controller *c, int step) +void fsl_ddr_set_memctl_regs(struct fsl_ddr_controller *c, int step, bool little_endian) { struct ccsr_ddr __iomem *ddr = c->base; const fsl_ddr_cfg_regs_t *regs = &c->fsl_ddr_config_reg; @@ -30,6 +30,11 @@ void fsl_ddr_set_memctl_regs(struct fsl_ddr_controller *c, int step) u32 total_gb_size_per_controller; int timeout; + if (little_endian) + ddr_endianess = DDR_ENDIANESS_LE; + else + ddr_endianess = DDR_ENDIANESS_BE; + if (step == 2) goto step2; diff --git a/drivers/ddr/fsl/fsl_ddr_gen4.c b/drivers/ddr/fsl/fsl_ddr_gen4.c index 147ff9916d..19aa4f22a9 100644 --- a/drivers/ddr/fsl/fsl_ddr_gen4.c +++ b/drivers/ddr/fsl/fsl_ddr_gen4.c @@ -36,7 +36,7 @@ static void set_wait_for_bits_clear(void *ptr, u32 value, u32 bits) * Dividing the initialization to two steps to deassert DDR reset signal * to comply with JEDEC specs for RDIMMs. */ -void fsl_ddr_set_memctl_regs(struct fsl_ddr_controller *c, int step) +void fsl_ddr_set_memctl_regs(struct fsl_ddr_controller *c, int step, bool little_endian) { struct ccsr_ddr __iomem *ddr = c->base; const fsl_ddr_cfg_regs_t *regs = &c->fsl_ddr_config_reg; @@ -53,6 +53,11 @@ void fsl_ddr_set_memctl_regs(struct fsl_ddr_controller *c, int step) u32 cs0_bnds, cs1_bnds, cs2_bnds, cs3_bnds, cs0_config; mod_bnds = regs->cs[0].config & CTLR_INTLV_MASK; + if (little_endian) + ddr_endianess = DDR_ENDIANESS_LE; + else + ddr_endianess = DDR_ENDIANESS_BE; + if (step == 2) goto step2; diff --git a/drivers/ddr/fsl/main.c b/drivers/ddr/fsl/main.c index c05f6d52fb..27303fec7e 100644 --- a/drivers/ddr/fsl/main.c +++ b/drivers/ddr/fsl/main.c @@ -13,6 +13,8 @@ #include <linux/log2.h> #include "fsl_ddr.h" +enum ddr_endianess ddr_endianess; + /* * ASSUMPTIONS: * - Same number of CONFIG_DIMM_SLOTS_PER_CTLR on each controller @@ -378,12 +380,17 @@ static unsigned long long fsl_ddr_compute(struct fsl_ddr_info *pinfo) return total_mem; } -phys_size_t fsl_ddr_sdram(struct fsl_ddr_info *pinfo) +phys_size_t fsl_ddr_sdram(struct fsl_ddr_info *pinfo, bool little_endian) { unsigned int i; unsigned long long total_memory; int deassert_reset = 0; + if (little_endian) + ddr_endianess = DDR_ENDIANESS_LE; + else + ddr_endianess = DDR_ENDIANESS_BE; + total_memory = fsl_ddr_compute(pinfo); /* setup 3-way interleaving before enabling DDRC */ @@ -428,14 +435,14 @@ phys_size_t fsl_ddr_sdram(struct fsl_ddr_info *pinfo) * The following call with step = 1 returns before enabling * the controller. It has to finish with step = 2 later. */ - fsl_ddr_set_memctl_regs(c, deassert_reset ? 1 : 0); + fsl_ddr_set_memctl_regs(c, deassert_reset ? 1 : 0, little_endian); } if (deassert_reset) { for (i = 0; i < pinfo->num_ctrls; i++) { struct fsl_ddr_controller *c = &pinfo->c[i]; /* Call with step = 2 to continue initialization */ - fsl_ddr_set_memctl_regs(c, 2); + fsl_ddr_set_memctl_regs(c, 2, little_endian); } } |