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| author | Ahmad Fatoum <a.fatoum@pengutronix.de> | 2023-07-06 18:16:40 +0200 |
|---|---|---|
| committer | Sascha Hauer <s.hauer@pengutronix.de> | 2023-07-26 15:38:14 +0200 |
| commit | e483a34a6b95f3e8849a2baad79d208632a3b46e (patch) | |
| tree | bced24fe9de11332c61c793dd3de700032daa85e /drivers/ddr | |
| parent | 2bd0681857370d2ae1bc8a53e7702ee55c658a41 (diff) | |
| download | barebox-e483a34a6b95f3e8849a2baad79d208632a3b46e.tar.gz barebox-e483a34a6b95f3e8849a2baad79d208632a3b46e.tar.xz | |
ddr: imx8m: add comment and print out prior to first DDRC read
If board code low level entry forgets to call imx8m*_early_clock_init
before DRAM setup, write access to DRAM controller will seem to work,
but the first read access will hang the system.
Make debugging this board bring up mistake easier by adding a debug
print along with a comment.
Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Reviewed-by: Marco Felsch <m.felsch@pengutronix.de>
Link: https://lore.barebox.org/20230706161640.843682-1-a.fatoum@pengutronix.de
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'drivers/ddr')
| -rw-r--r-- | drivers/ddr/imx8m/ddr_init.c | 6 |
1 files changed, 5 insertions, 1 deletions
diff --git a/drivers/ddr/imx8m/ddr_init.c b/drivers/ddr/imx8m/ddr_init.c index 944cc3873e..9a86280d9c 100644 --- a/drivers/ddr/imx8m/ddr_init.c +++ b/drivers/ddr/imx8m/ddr_init.c @@ -106,7 +106,11 @@ int imx8m_ddr_init(struct dram_timing_info *dram_timing, reg32_write(DDRC_RFSHCTL3(0), 0x0000001); reg32_write(DDRC_PWRCTL(0), 0xa0); - /* if ddr type is LPDDR4, do it */ + pr_debug("checking ddr type\n"); + /* + * below is first read, so if boot hangs here, imx8m*_early_clock_init() + * might not have been called + */ tmp = reg32_read(DDRC_MSTR(0)); if (tmp & (0x1 << 5) && ddrc_type != DDRC_TYPE_MN) reg32_write(DDRC_DDR_SS_GPR0, 0x01); /* LPDDR4 mode */ |