ARM: i.MX8M: include only necessary ddrphy firmwares in image

So far we always include ddrphy firmwares for DDR4 and LPDDR4 in the
images. Pass the DDR type to the RAM controller initialization so
that the type is known at compile time. With this the compiler can
discard the unused firmware files.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

2 files changed, 60 insertions, 30 deletions

diff --git a/drivers/ddr/imx8m/ddr_init.c b/drivers/ddr/imx8m/ddr_init.c
index 9a4b4e2ca8..41e1fba38a 100644
--- a/drivers/ddr/imx8m/ddr_init.c
+++ b/drivers/ddr/imx8m/ddr_init.c
@@ -49,8 +49,8 @@ static void ddr_cfg_umctl2(struct dram_cfg_param *ddrc_cfg, int num)
  */
 #define IMX8M_SAVED_DRAM_TIMING_BASE		0x180000
 
-static int imx8m_ddr_init(struct dram_timing_info *dram_timing,
-			  enum ddrc_type type)
+int imx8m_ddr_init(struct dram_timing_info *dram_timing,
+		   enum ddrc_type type)
 {
 	unsigned long src_ddrc_rcr = MX8M_SRC_DDRC_RCR_ADDR;
 	unsigned int tmp, initial_drate, target_freq;
@@ -210,23 +210,3 @@ static int imx8m_ddr_init(struct dram_timing_info *dram_timing,
 
 	return 0;
 }
-
-int imx8mm_ddr_init(struct dram_timing_info *dram_timing)
-{
-	return imx8m_ddr_init(dram_timing, DDRC_TYPE_MM);
-}
-
-int imx8mn_ddr_init(struct dram_timing_info *dram_timing)
-{
-	return imx8m_ddr_init(dram_timing, DDRC_TYPE_MN);
-}
-
-int imx8mq_ddr_init(struct dram_timing_info *dram_timing)
-{
-	return imx8m_ddr_init(dram_timing, DDRC_TYPE_MQ);
-}
-
-int imx8mp_ddr_init(struct dram_timing_info *dram_timing)
-{
-	return imx8m_ddr_init(dram_timing, DDRC_TYPE_MP);
-}
diff --git a/drivers/ddr/imx8m/ddrphy_train.c b/drivers/ddr/imx8m/ddrphy_train.c
index 9dc20a4762..2190b53413 100644
--- a/drivers/ddr/imx8m/ddrphy_train.c
+++ b/drivers/ddr/imx8m/ddrphy_train.c
@@ -11,6 +11,48 @@
 #include <firmware.h>
 #include <mach/imx8m-regs.h>
 
+static const u16 *lpddr4_imem_1d;
+static size_t lpddr4_imem_1d_size;
+static const u16 *lpddr4_dmem_1d;
+static size_t lpddr4_dmem_1d_size;
+static const u16 *lpddr4_imem_2d;
+static size_t lpddr4_imem_2d_size;
+static const u16 *lpddr4_dmem_2d;
+static size_t lpddr4_dmem_2d_size;
+
+void ddr_get_firmware_lpddr4(void)
+{
+	get_builtin_firmware(lpddr4_pmu_train_1d_imem_bin, &lpddr4_imem_1d,
+			     &lpddr4_imem_1d_size);
+	get_builtin_firmware(lpddr4_pmu_train_1d_dmem_bin, &lpddr4_dmem_1d,
+			     &lpddr4_dmem_1d_size);
+	get_builtin_firmware(lpddr4_pmu_train_2d_imem_bin, &lpddr4_imem_2d,
+			     &lpddr4_imem_2d_size);
+	get_builtin_firmware(lpddr4_pmu_train_2d_dmem_bin, &lpddr4_dmem_2d,
+			     &lpddr4_dmem_2d_size);
+}
+
+static const u16 *ddr4_imem_1d;
+static size_t ddr4_imem_1d_size;
+static const u16 *ddr4_dmem_1d;
+static size_t ddr4_dmem_1d_size;
+static const u16 *ddr4_imem_2d;
+static size_t ddr4_imem_2d_size;
+static const u16 *ddr4_dmem_2d;
+static size_t ddr4_dmem_2d_size;
+
+void ddr_get_firmware_ddr(void)
+{
+	get_builtin_firmware(ddr4_imem_1d_bin, &ddr4_imem_1d,
+			     &ddr4_imem_1d_size);
+	get_builtin_firmware(ddr4_dmem_1d_bin, &ddr4_dmem_1d,
+			     &ddr4_dmem_1d_size);
+	get_builtin_firmware(ddr4_imem_2d_bin, &ddr4_imem_2d,
+			     &ddr4_imem_2d_size);
+	get_builtin_firmware(ddr4_dmem_2d_bin, &ddr4_dmem_2d,
+			     &ddr4_dmem_2d_size);
+}
+
 void ddr_load_train_code(enum dram_type dram_type, enum fw_type fw_type)
 {
 	const u16 *imem, *dmem;
@@ -18,19 +60,27 @@ void ddr_load_train_code(enum dram_type dram_type, enum fw_type fw_type)
 
 	if (dram_is_lpddr4(dram_type)) {
 		if (fw_type == FW_1D_IMAGE) {
-			get_builtin_firmware(lpddr4_pmu_train_1d_imem_bin, &imem, &isize);
-			get_builtin_firmware(lpddr4_pmu_train_1d_dmem_bin, &dmem, &dsize);
+			imem = lpddr4_imem_1d;
+			isize = lpddr4_imem_1d_size;
+			dmem = lpddr4_dmem_1d;
+			dsize = lpddr4_dmem_1d_size;
 		} else {
-			get_builtin_firmware(lpddr4_pmu_train_2d_imem_bin, &imem, &isize);
-			get_builtin_firmware(lpddr4_pmu_train_2d_dmem_bin, &dmem, &dsize);
+			imem = lpddr4_imem_2d;
+			isize = lpddr4_imem_2d_size;
+			dmem = lpddr4_dmem_2d;
+			dsize = lpddr4_dmem_2d_size;
 		}
 	} else if (dram_is_ddr4(dram_type)) {
 		if (fw_type == FW_1D_IMAGE) {
-			get_builtin_firmware(ddr4_imem_1d_bin, &imem, &isize);
-			get_builtin_firmware(ddr4_dmem_1d_bin, &dmem, &dsize);
+			imem = ddr4_imem_1d;
+			isize = ddr4_imem_1d_size;
+			dmem = ddr4_dmem_1d;
+			dsize = ddr4_dmem_1d_size;
 		} else {
-			get_builtin_firmware(ddr4_imem_2d_bin, &imem, &isize);
-			get_builtin_firmware(ddr4_dmem_2d_bin, &dmem, &dsize);
+			imem = ddr4_imem_2d;
+			isize = ddr4_imem_2d_size;
+			dmem = ddr4_dmem_2d;
+			dsize = ddr4_dmem_2d_size;
 		}
 	} else {
 		panic("No matching DDR PHY firmware found");