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| author | Sascha Hauer <s.hauer@pengutronix.de> | 2013-04-24 09:28:00 +0200 |
|---|---|---|
| committer | Sascha Hauer <s.hauer@pengutronix.de> | 2013-05-30 12:18:27 +0200 |
| commit | bd1bf53b34c62fa69ae5922a660643c6e5febf06 (patch) | |
| tree | 0b56edd6e8e308a8461056126fbbbfc18342922b /drivers/mci/imx-esdhc.h | |
| parent | a6afae76f10989fddc2b45ec12c21fa5e920d6aa (diff) | |
| download | barebox-bd1bf53b34c62fa69ae5922a660643c6e5febf06.tar.gz barebox-bd1bf53b34c62fa69ae5922a660643c6e5febf06.tar.xz | |
mci: imx-esdhc: factor out common sdhci registers
This gives the SDHCI specific registers a common name and moves
them to a separate file for use by other SDHCI like drivers.
The SDHCI spec has some 16bit and 8bit registers. The i.MX accesses
these as 32bit registers. These register defines now are named after
the SDHCI registers they combine into one, for example:
SDHCI_HOST_CONTROL__POWER_CONTROL__BLOCK_GAP_CONTROL
is the 32bit version of the SDHCI registers HOST_CONTROL, POWER_CONTROL
and BLOCK_GAP_CONTROL.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'drivers/mci/imx-esdhc.h')
| -rw-r--r-- | drivers/mci/imx-esdhc.h | 89 |
1 files changed, 0 insertions, 89 deletions
diff --git a/drivers/mci/imx-esdhc.h b/drivers/mci/imx-esdhc.h index 2be63a5ba0..ea1cb318e5 100644 --- a/drivers/mci/imx-esdhc.h +++ b/drivers/mci/imx-esdhc.h @@ -25,8 +25,6 @@ #include <errno.h> #include <asm/byteorder.h> -/* FSL eSDHC-specific constants */ -#define SYSCTL 0x0002e02c #define SYSCTL_INITA 0x08000000 #define SYSCTL_TIMEOUT_MASK 0x000f0000 #define SYSCTL_CLOCK_MASK 0x0000fff0 @@ -36,104 +34,17 @@ #define SYSCTL_HCKEN 0x00000002 #define SYSCTL_IPGEN 0x00000001 -#define IRQSTAT 0x0002e030 -#define IRQSTAT_DMAE (0x10000000) -#define IRQSTAT_AC12E (0x01000000) -#define IRQSTAT_DEBE (0x00400000) -#define IRQSTAT_DCE (0x00200000) -#define IRQSTAT_DTOE (0x00100000) -#define IRQSTAT_CIE (0x00080000) -#define IRQSTAT_CEBE (0x00040000) -#define IRQSTAT_CCE (0x00020000) -#define IRQSTAT_CTOE (0x00010000) -#define IRQSTAT_CINT (0x00000100) -#define IRQSTAT_CRM (0x00000080) -#define IRQSTAT_CINS (0x00000040) -#define IRQSTAT_BRR (0x00000020) -#define IRQSTAT_BWR (0x00000010) -#define IRQSTAT_DINT (0x00000008) -#define IRQSTAT_BGE (0x00000004) -#define IRQSTAT_TC (0x00000002) -#define IRQSTAT_CC (0x00000001) - #define CMD_ERR (IRQSTAT_CIE | IRQSTAT_CEBE | IRQSTAT_CCE) #define DATA_ERR (IRQSTAT_DEBE | IRQSTAT_DCE | IRQSTAT_DTOE) -#define IRQSTATEN 0x0002e034 -#define IRQSTATEN_DMAE (0x10000000) -#define IRQSTATEN_AC12E (0x01000000) -#define IRQSTATEN_DEBE (0x00400000) -#define IRQSTATEN_DCE (0x00200000) -#define IRQSTATEN_DTOE (0x00100000) -#define IRQSTATEN_CIE (0x00080000) -#define IRQSTATEN_CEBE (0x00040000) -#define IRQSTATEN_CCE (0x00020000) -#define IRQSTATEN_CTOE (0x00010000) -#define IRQSTATEN_CINT (0x00000100) -#define IRQSTATEN_CRM (0x00000080) -#define IRQSTATEN_CINS (0x00000040) -#define IRQSTATEN_BRR (0x00000020) -#define IRQSTATEN_BWR (0x00000010) -#define IRQSTATEN_DINT (0x00000008) -#define IRQSTATEN_BGE (0x00000004) -#define IRQSTATEN_TC (0x00000002) -#define IRQSTATEN_CC (0x00000001) - -#define PRSSTAT 0x0002e024 -#define PRSSTAT_CLSL (0x00800000) -#define PRSSTAT_WPSPL (0x00080000) -#define PRSSTAT_CDPL (0x00040000) -#define PRSSTAT_CINS (0x00010000) -#define PRSSTAT_BREN (0x00000800) -#define PRSSTAT_BWEN (0x00000400) -#define PRSSTAT_DLA (0x00000004) -#define PRSSTAT_CICHB (0x00000002) -#define PRSSTAT_CIDHB (0x00000001) - -#define PROCTL 0x0002e028 #define PROCTL_INIT 0x00000020 #define PROCTL_DTW_4 0x00000002 #define PROCTL_DTW_8 0x00000004 -#define CMDARG 0x0002e008 - -#define XFERTYP 0x0002e00c -#define XFERTYP_CMD(x) ((x & 0x3f) << 24) -#define XFERTYP_CMDTYP_NORMAL 0x0 -#define XFERTYP_CMDTYP_SUSPEND 0x00400000 -#define XFERTYP_CMDTYP_RESUME 0x00800000 -#define XFERTYP_CMDTYP_ABORT 0x00c00000 -#define XFERTYP_DPSEL 0x00200000 -#define XFERTYP_CICEN 0x00100000 -#define XFERTYP_CCCEN 0x00080000 -#define XFERTYP_RSPTYP_NONE 0 -#define XFERTYP_RSPTYP_136 0x00010000 -#define XFERTYP_RSPTYP_48 0x00020000 -#define XFERTYP_RSPTYP_48_BUSY 0x00030000 -#define XFERTYP_MSBSEL 0x00000020 -#define XFERTYP_DTDSEL 0x00000010 -#define XFERTYP_AC12EN 0x00000004 -#define XFERTYP_BCEN 0x00000002 -#define XFERTYP_DMAEN 0x00000001 - -#define CINS_TIMEOUT 1000 -#define PIO_TIMEOUT 100000 - -#define DSADDR 0x2e004 - -#define CMDRSP0 0x2e010 -#define CMDRSP1 0x2e014 -#define CMDRSP2 0x2e018 -#define CMDRSP3 0x2e01c - -#define DATPORT 0x2e020 - -#define WML 0x2e044 #define WML_WRITE 0x00010000 #define WML_RD_WML_MASK 0xff #define WML_WR_WML_MASK 0xff0000 -#define BLKATTR 0x2e004 #define BLKATTR_CNT(x) ((x & 0xffff) << 16) #define BLKATTR_SIZE(x) (x & 0x1fff) #define MAX_BLK_CNT 0x7fff /* so malloc will have enough room with 32M */ |