mci: imx-esdhc: factor out common sdhci registers

This gives the SDHCI specific registers a common name and moves
them to a separate file for use by other SDHCI like drivers.

The SDHCI spec has some 16bit and 8bit registers. The i.MX accesses
these as 32bit registers. These register defines now are named after
the SDHCI registers they combine into one, for example:

SDHCI_HOST_CONTROL__POWER_CONTROL__BLOCK_GAP_CONTROL

is the 32bit version of the SDHCI registers HOST_CONTROL, POWER_CONTROL
and BLOCK_GAP_CONTROL.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

1 files changed, 88 insertions, 0 deletions

diff --git a/drivers/mci/sdhci.h b/drivers/mci/sdhci.h
new file mode 100644
index 0000000000..ad1bbd96e3
--- /dev/null
+++ b/drivers/mci/sdhci.h
@@ -0,0 +1,88 @@
+#ifndef __MCI_SDHCI_H
+#define __MCI_SDHCI_H
+
+#define SDHCI_DMA_ADDRESS					0x00
+#define SDHCI_BLOCK_SIZE__BLOCK_COUNT				0x04
+#define SDHCI_ARGUMENT						0x08
+#define SDHCI_TRANSFER_MODE__COMMAND				0x0c
+#define SDHCI_RESPONSE_0					0x10
+#define SDHCI_RESPONSE_1					0x14
+#define SDHCI_RESPONSE_2					0x18
+#define SDHCI_RESPONSE_3					0x1c
+#define SDHCI_BUFFER						0x20
+#define SDHCI_PRESENT_STATE					0x24
+#define SDHCI_HOST_CONTROL__POWER_CONTROL__BLOCK_GAP_CONTROL	0x28
+#define SDHCI_CLOCK_CONTROL__TIMEOUT_CONTROL__SOFTWARE_RESET	0x2c
+#define SDHCI_INT_STATUS					0x30
+#define SDHCI_INT_ENABLE					0x34
+#define SDHCI_SIGNAL_ENABLE					0x38
+#define SDHCI_ACMD12_ERR__HOST_CONTROL2				0x3C
+#define SDHCI_CAPABILITIES					0x40
+
+#define COMMAND_CMD(x)		((x & 0x3f) << 24)
+#define COMMAND_CMDTYP_NORMAL	0x0
+#define COMMAND_CMDTYP_SUSPEND	0x00400000
+#define COMMAND_CMDTYP_RESUME	0x00800000
+#define COMMAND_CMDTYP_ABORT	0x00c00000
+#define COMMAND_DPSEL		0x00200000
+#define COMMAND_CICEN		0x00100000
+#define COMMAND_CCCEN		0x00080000
+#define COMMAND_RSPTYP_NONE	0
+#define COMMAND_RSPTYP_136	0x00010000
+#define COMMAND_RSPTYP_48	0x00020000
+#define COMMAND_RSPTYP_48_BUSY	0x00030000
+#define TRANSFER_MODE_MSBSEL	0x00000020
+#define TRANSFER_MODE_DTDSEL	0x00000010
+#define TRANSFER_MODE_AC12EN	0x00000004
+#define TRANSFER_MODE_BCEN	0x00000002
+#define TRANSFER_MODE_DMAEN	0x00000001
+
+#define IRQSTAT_DMAE		0x10000000
+#define IRQSTAT_AC12E		0x01000000
+#define IRQSTAT_DEBE		0x00400000
+#define IRQSTAT_DCE		0x00200000
+#define IRQSTAT_DTOE		0x00100000
+#define IRQSTAT_CIE		0x00080000
+#define IRQSTAT_CEBE		0x00040000
+#define IRQSTAT_CCE		0x00020000
+#define IRQSTAT_CTOE		0x00010000
+#define IRQSTAT_CINT		0x00000100
+#define IRQSTAT_CRM		0x00000080
+#define IRQSTAT_CINS		0x00000040
+#define IRQSTAT_BRR		0x00000020
+#define IRQSTAT_BWR		0x00000010
+#define IRQSTAT_DINT		0x00000008
+#define IRQSTAT_BGE		0x00000004
+#define IRQSTAT_TC		0x00000002
+#define IRQSTAT_CC		0x00000001
+
+#define IRQSTATEN_DMAE		0x10000000
+#define IRQSTATEN_AC12E		0x01000000
+#define IRQSTATEN_DEBE		0x00400000
+#define IRQSTATEN_DCE		0x00200000
+#define IRQSTATEN_DTOE		0x00100000
+#define IRQSTATEN_CIE		0x00080000
+#define IRQSTATEN_CEBE		0x00040000
+#define IRQSTATEN_CCE		0x00020000
+#define IRQSTATEN_CTOE		0x00010000
+#define IRQSTATEN_CINT		0x00000100
+#define IRQSTATEN_CRM		0x00000080
+#define IRQSTATEN_CINS		0x00000040
+#define IRQSTATEN_BRR		0x00000020
+#define IRQSTATEN_BWR		0x00000010
+#define IRQSTATEN_DINT		0x00000008
+#define IRQSTATEN_BGE		0x00000004
+#define IRQSTATEN_TC		0x00000002
+#define IRQSTATEN_CC		0x00000001
+
+#define PRSSTAT_CLSL		0x00800000
+#define PRSSTAT_WPSPL		0x00080000
+#define PRSSTAT_CDPL		0x00040000
+#define PRSSTAT_CINS		0x00010000
+#define PRSSTAT_BREN		0x00000800
+#define PRSSTAT_BWEN		0x00000400
+#define PRSSTAT_DLA		0x00000004
+#define PRSSTAT_CIDHB		0x00000002
+#define PRSSTAT_CICHB		0x00000001
+
+#endif /* __MCI_SDHCI_H */