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| author | Andrey Smirnov <andrew.smirnov@gmail.com> | 2019-01-13 22:16:54 -0800 |
|---|---|---|
| committer | Sascha Hauer <s.hauer@pengutronix.de> | 2019-01-16 08:36:18 +0100 |
| commit | 1c26a4a29f134fcbcbc0056ea6f590061d6e5062 (patch) | |
| tree | 2b8dd5221521e81bcf594a75c4a15dedc95d16ee /drivers/pci | |
| parent | 31551c89701c42f63d3f4352ed84e7842d0ba9fe (diff) | |
| download | barebox-1c26a4a29f134fcbcbc0056ea6f590061d6e5062.tar.gz barebox-1c26a4a29f134fcbcbc0056ea6f590061d6e5062.tar.xz | |
PCI: Switch to using %pa to print memory addresses
Switch to using %pa to print memory addresses in order to be able to
support both 64 and 32 bit builds.
Reviewed-by: Sam Ravnborg <sam@ravnborg.org>
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'drivers/pci')
| -rw-r--r-- | drivers/pci/pci.c | 16 |
1 files changed, 8 insertions, 8 deletions
diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c index 7abc7a3439..1f9d360d79 100644 --- a/drivers/pci/pci.c +++ b/drivers/pci/pci.c @@ -195,7 +195,7 @@ static void setup_device(struct pci_dev *dev, int max_bar) return; } last_io = ALIGN(last_io, size); - pr_debug("pbar%d: allocated at 0x%08x\n", bar, last_io); + pr_debug("pbar%d: allocated at %pa\n", bar, &last_io); pci_write_config_dword(dev, PCI_BASE_ADDRESS_0 + bar * 4, last_io); dev->resource[bar].flags = IORESOURCE_IO; last_addr = last_io; @@ -215,7 +215,7 @@ static void setup_device(struct pci_dev *dev, int max_bar) return; } last_mem_pref = ALIGN(last_mem_pref, size); - pr_debug("pbar%d: allocated at 0x%08x\n", bar, last_mem_pref); + pr_debug("pbar%d: allocated at %pa\n", bar, &last_mem_pref); pci_write_config_dword(dev, PCI_BASE_ADDRESS_0 + bar * 4, last_mem_pref); dev->resource[bar].flags = IORESOURCE_MEM | IORESOURCE_PREFETCH; @@ -235,7 +235,7 @@ static void setup_device(struct pci_dev *dev, int max_bar) return; } last_mem = ALIGN(last_mem, size); - pr_debug("pbar%d: allocated at 0x%08x\n", bar, last_mem); + pr_debug("pbar%d: allocated at %pa\n", bar, &last_mem); pci_write_config_dword(dev, PCI_BASE_ADDRESS_0 + bar * 4, last_mem); dev->resource[bar].flags = IORESOURCE_MEM; last_addr = last_mem; @@ -311,21 +311,21 @@ static void postscan_setup_bridge(struct pci_dev *dev) if (last_mem) { last_mem = ALIGN(last_mem, SZ_1M); - pr_debug("bridge NP limit at 0x%08x\n", last_mem); + pr_debug("bridge NP limit at %pa\n", &last_mem); pci_write_config_word(dev, PCI_MEMORY_LIMIT, ((last_mem - 1) & 0xfff00000) >> 16); } if (last_mem_pref) { last_mem_pref = ALIGN(last_mem_pref, SZ_1M); - pr_debug("bridge P limit at 0x%08x\n", last_mem_pref); + pr_debug("bridge P limit at %pa\n", &last_mem_pref); pci_write_config_word(dev, PCI_PREF_MEMORY_LIMIT, ((last_mem_pref - 1) & 0xfff00000) >> 16); } if (last_io) { last_io = ALIGN(last_io, SZ_4K); - pr_debug("bridge IO limit at 0x%08x\n", last_io); + pr_debug("bridge IO limit at %pa\n", &last_io); pci_write_config_byte(dev, PCI_IO_LIMIT, ((last_io - 1) & 0x0000f000) >> 8); pci_write_config_word(dev, PCI_IO_LIMIT_UPPER16, @@ -366,8 +366,8 @@ unsigned int pci_scan_bus(struct pci_bus *bus) unsigned char cmd, tmp, hdr_type, is_multi = 0; pr_debug("pci_scan_bus for bus %d\n", bus->number); - pr_debug(" last_io = 0x%08x, last_mem = 0x%08x, last_mem_pref = 0x%08x\n", - last_io, last_mem, last_mem_pref); + pr_debug(" last_io = %pa, last_mem = %pa, last_mem_pref = %pa\n", + &last_io, &last_mem, &last_mem_pref); max = bus->secondary; |