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authorJuergen Beisert <jbe@pengutronix.de>2012-07-24 11:24:51 +0200
committerSascha Hauer <s.hauer@pengutronix.de>2012-07-25 09:27:39 +0200
commit1fdb1cf1c4f70f70f5f4bee1f2eeda31ed544f0c (patch)
tree5bccdde37085cc8dc4a761b4e09c3697d2620d31 /drivers/serial/serial_s3c.c
parent24c110da94f4d0d764ec191e239bec4696ca637f (diff)
downloadbarebox-1fdb1cf1c4f70f70f5f4bee1f2eeda31ed544f0c.tar.gz
barebox-1fdb1cf1c4f70f70f5f4bee1f2eeda31ed544f0c.tar.xz
Samsung/serial: make the clock source configureable
Instead of taking the value from somewhere, use the selected architecture to select one. This ensures the selected clock source corresponds to the values setup in the clocks-*.c from the mach directory. Signed-off-by: Juergen Beisert <jbe@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'drivers/serial/serial_s3c.c')
-rw-r--r--drivers/serial/serial_s3c.c18
1 files changed, 12 insertions, 6 deletions
diff --git a/drivers/serial/serial_s3c.c b/drivers/serial/serial_s3c.c
index 96fe84744f..0a7b137d19 100644
--- a/drivers/serial/serial_s3c.c
+++ b/drivers/serial/serial_s3c.c
@@ -45,11 +45,6 @@
#define UBRDIVSLOT 0x2c /* baudrate slot generator */
#define UINTM 0x38 /* interrupt mask register */
-#ifndef S3C_UART_CLKSEL
-/* Use pclk */
-# define S3C_UART_CLKSEL 0
-#endif
-
struct s3c_uart {
void __iomem *regs;
struct console_device cdev;
@@ -57,6 +52,17 @@ struct s3c_uart {
#define to_s3c_uart(c) container_of(c, struct s3c_uart, cdev)
+/* each architecture has a preferred reference clock for its UARTs */
+static unsigned s3c_select_arch_input_clock(void)
+{
+ /* S3C24xx: 0=2=PCLK, 1=UEXTCLK, 3=FCLK/n */
+ if (IS_ENABLED(CONFIG_ARCH_S3C24xx))
+ return 0; /* use the internal PCLK */
+ /* S5PCxx: 0=PCLK, 1=SCLK_UART */
+ if (IS_ENABLED(CONFIG_ARCH_S5PCxx))
+ return 0; /* use the internal PCLK */
+}
+
static unsigned s3c_get_arch_uart_input_clock(void __iomem *base)
{
unsigned reg = readw(base + UCON);
@@ -108,7 +114,7 @@ static int s3c_serial_init_port(struct console_device *cdev)
* all SoCs:
* - enable receive and transmit mode
*/
- writew(0x0005 | UCON_SET_CLK_SRC(S3C_UART_CLKSEL),
+ writew(0x0005 | UCON_SET_CLK_SRC(s3c_select_arch_input_clock()),
base + UCON);
if (IS_ENABLED(CONFIG_DRIVER_SERIAL_S3C_IMPROVED))