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authorLucas Stach <dev@lynxeye.de>2019-11-01 20:54:29 +0100
committerSascha Hauer <s.hauer@pengutronix.de>2019-11-04 09:58:08 +0100
commit24ff6d5a11c5f79701292c8ee9827ee724ffce4a (patch)
tree9b0876dc6162d1dce917ece51430fef8a3030006 /drivers/serial
parent8685748d34c68e1b6d446bbe1a481ac257b0cb6c (diff)
downloadbarebox-24ff6d5a11c5f79701292c8ee9827ee724ffce4a.tar.gz
serial: cadence: fix serial_flush
The TXEMPTY bit gets set as soon as the transmit FIFO gets empty, so flushing must wait until the bit is set instead of being unset. Signed-off-by: Lucas Stach <dev@lynxeye.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'drivers/serial')
-rw-r--r--drivers/serial/serial_cadence.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/serial/serial_cadence.c b/drivers/serial/serial_cadence.c
index 0501c40..6454888 100644
--- a/drivers/serial/serial_cadence.c
+++ b/drivers/serial/serial_cadence.c
@@ -199,7 +199,7 @@ static void cadence_serial_flush(struct console_device *cdev)
struct cadence_serial_priv, cdev);
while ((readl(priv->regs + CADENCE_UART_CHANNEL_STS) &
- CADENCE_STS_TEMPTY) != 0)
+ CADENCE_STS_TEMPTY) == 0)
;
}