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| author | Ahmad Fatoum <a.fatoum@pengutronix.de> | 2024-04-02 15:44:59 +0200 |
|---|---|---|
| committer | Sascha Hauer <s.hauer@pengutronix.de> | 2024-04-03 13:32:04 +0200 |
| commit | 046ceb972493867fef309e523f646fa51175ee0a (patch) | |
| tree | b0565e20eddcb5ab377f8ac181fbc275c243513f /drivers/soc | |
| parent | 5423885658da4beddec619c1ec4b1cb741c68554 (diff) | |
| download | barebox-046ceb972493867fef309e523f646fa51175ee0a.tar.gz barebox-046ceb972493867fef309e523f646fa51175ee0a.tar.xz | |
soc: sifive: l2_cache: fix 32-bit compilation
The StarFive SoCs are 64-bit, but the L2 cache driver could be
compile-tested on 32-bit as well. Currently, this would fail, because
writeq isn't defined. Fix this by emulating it using a lo-hi write.
Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Link: https://lore.barebox.org/20240402134501.3689322-1-a.fatoum@pengutronix.de
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'drivers/soc')
| -rw-r--r-- | drivers/soc/sifive/sifive_l2_cache.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/soc/sifive/sifive_l2_cache.c b/drivers/soc/sifive/sifive_l2_cache.c index aab21f9f50..c404143974 100644 --- a/drivers/soc/sifive/sifive_l2_cache.c +++ b/drivers/soc/sifive/sifive_l2_cache.c @@ -9,6 +9,7 @@ #define pr_fmt(fmt) "sifive-l2: " fmt #include <io.h> +#include <io-64-nonatomic-lo-hi.h> #include <linux/printk.h> #include <stdio.h> #include <driver.h> |