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| author | Ahmad Fatoum <a.fatoum@pengutronix.de> | 2021-10-01 12:09:47 +0200 |
|---|---|---|
| committer | Sascha Hauer <s.hauer@pengutronix.de> | 2021-10-05 09:05:37 +0200 |
| commit | 51140eec25a489d1259d24814af5aaa2c09f82b1 (patch) | |
| tree | 349dd0de4d93967b0331e12374d8b147ed637758 /drivers | |
| parent | 36b5417fe6f0fce432fb219edef996891336179c (diff) | |
| download | barebox-51140eec25a489d1259d24814af5aaa2c09f82b1.tar.gz barebox-51140eec25a489d1259d24814af5aaa2c09f82b1.tar.xz | |
ddr: imx8m: ddrphy_train: add DDR4 support
There are DDR3L, DDR4 and LPDDR4 variants of the i.MX8M* SoMs used with
the NXP EVKs. So far, we only supported LPDDR4. For DDR4, we just need
different PHY training code. Encode the DRAM variant information
into a new dram_timing_info::dram_type and adjust the driver to make use
of it. The new CONFIG_FIRMWARE_IMX_DDR4_PMU_TRAIN Kconfig symbol can
co-exist with CONFIG_FIRMWARE_IMX_LPDDR4_PMU_TRAIN, allowing the same
barebox binary to target different memory types, provided board code
can determine what kind of DRAM is fitted.
Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Link: https://lore.barebox.org/20211001100949.6891-7-a.fatoum@pengutronix.de
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'drivers')
| -rw-r--r-- | drivers/ddr/imx8m/ddrphy_train.c | 26 |
1 files changed, 19 insertions, 7 deletions
diff --git a/drivers/ddr/imx8m/ddrphy_train.c b/drivers/ddr/imx8m/ddrphy_train.c index a4677f903c..d930a2fffe 100644 --- a/drivers/ddr/imx8m/ddrphy_train.c +++ b/drivers/ddr/imx8m/ddrphy_train.c @@ -11,17 +11,29 @@ #include <firmware.h> #include <mach/imx8m-regs.h> -void ddr_load_train_code(enum fw_type type) +void ddr_load_train_code(enum dram_type dram_type, enum fw_type fw_type) { const u16 *imem, *dmem; size_t isize, dsize; - if (type == FW_1D_IMAGE) { - get_builtin_firmware(lpddr4_pmu_train_1d_imem_bin, &imem, &isize); - get_builtin_firmware(lpddr4_pmu_train_1d_dmem_bin, &dmem, &dsize); + if (dram_is_lpddr4(dram_type)) { + if (fw_type == FW_1D_IMAGE) { + get_builtin_firmware(lpddr4_pmu_train_1d_imem_bin, &imem, &isize); + get_builtin_firmware(lpddr4_pmu_train_1d_dmem_bin, &dmem, &dsize); + } else { + get_builtin_firmware(lpddr4_pmu_train_2d_imem_bin, &imem, &isize); + get_builtin_firmware(lpddr4_pmu_train_2d_dmem_bin, &dmem, &dsize); + } + } else if (dram_is_ddr4(dram_type)) { + if (fw_type == FW_1D_IMAGE) { + get_builtin_firmware(ddr4_imem_1d_bin, &imem, &isize); + get_builtin_firmware(ddr4_dmem_1d_bin, &dmem, &dsize); + } else { + get_builtin_firmware(ddr4_imem_2d_bin, &imem, &isize); + get_builtin_firmware(ddr4_dmem_2d_bin, &dmem, &dsize); + } } else { - get_builtin_firmware(lpddr4_pmu_train_2d_imem_bin, &imem, &isize); - get_builtin_firmware(lpddr4_pmu_train_2d_dmem_bin, &dmem, &dsize); + panic("No matching DDR PHY firmware found"); } ddrc_phy_load_firmware(IOMEM(MX8M_DDRC_PHY_BASE_ADDR), @@ -58,7 +70,7 @@ int ddr_cfg_phy(struct dram_timing_info *dram_timing, enum ddrc_type type) /* load the dram training firmware image */ dwc_ddrphy_apb_wr(0xd0000, 0x0); - ddr_load_train_code(fsp_msg->fw_type); + ddr_load_train_code(dram_timing->dram_type, fsp_msg->fw_type); /* load the frequency set point message block parameter */ dram_cfg = fsp_msg->fsp_cfg; |