mci: sdhci: Use Linux defines for SDHCI_HOST_CONTROL register

To ease porting and comparing of Linux code.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Link: https://lore.barebox.org/20210607104411.23071-7-s.hauer@pengutronix.de
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

4 files changed, 30 insertions, 23 deletions

diff --git a/drivers/mci/arasan-sdhci.c b/drivers/mci/arasan-sdhci.c
index ca72e3aec9..ea81bcb122 100644
--- a/drivers/mci/arasan-sdhci.c
+++ b/drivers/mci/arasan-sdhci.c
@@ -124,7 +124,7 @@ static int arasan_sdhci_reset(struct arasan_sdhci_host *host, u8 mask)
 		u8 ctrl;
 
 		ctrl = sdhci_read8(&host->sdhci, SDHCI_HOST_CONTROL);
-		ctrl |= SDHCI_CARD_DETECT_TEST_LEVEL | SDHCI_CARD_DETECT_SIGNAL_SELECTION;
+		ctrl |= SDHCI_CTRL_CDTEST_INS | SDHCI_CTRL_CDTEST_INS;
 		sdhci_write8(&host->sdhci, ctrl, SDHCI_HOST_CONTROL);
 	}
 
@@ -200,21 +200,21 @@ static void arasan_sdhci_set_ios(struct mci_host *mci, struct mci_ios *ios)
 	}
 
 	val = sdhci_read8(&host->sdhci, SDHCI_HOST_CONTROL) &
-			~(SDHCI_DATA_WIDTH_4BIT | SDHCI_DATA_WIDTH_8BIT);
+			~(SDHCI_CTRL_8BITBUS | SDHCI_CTRL_8BITBUS);
 
 	switch (ios->bus_width) {
 	case MMC_BUS_WIDTH_8:
-		val |= SDHCI_DATA_WIDTH_8BIT;
+		val |= SDHCI_CTRL_8BITBUS;
 		break;
 	case MMC_BUS_WIDTH_4:
-		val |= SDHCI_DATA_WIDTH_4BIT;
+		val |= SDHCI_CTRL_8BITBUS;
 		break;
 	}
 
 	if (ios->clock > 26000000)
-		val |= SDHCI_HIGHSPEED_EN;
+		val |= SDHCI_CTRL_HISPD;
 	else
-		val &= ~SDHCI_HIGHSPEED_EN;
+		val &= ~SDHCI_CTRL_HISPD;
 
 	sdhci_write8(&host->sdhci, SDHCI_HOST_CONTROL, val);
 }
diff --git a/drivers/mci/atmel-sdhci-common.c b/drivers/mci/atmel-sdhci-common.c
index 6b7fca7f34..6d8c77dd4f 100644
--- a/drivers/mci/atmel-sdhci-common.c
+++ b/drivers/mci/atmel-sdhci-common.c
@@ -280,9 +280,9 @@ static int at91_sdhci_set_clock(struct at91_sdhci *host, unsigned clock)
 
 	reg = sdhci_read8(sdhci, SDHCI_HOST_CONTROL);
 	if (clock > 26000000)
-		reg |= SDHCI_HIGHSPEED_EN;
+		reg |= SDHCI_CTRL_HISPD;
 	else
-		reg &= ~SDHCI_HIGHSPEED_EN;
+		reg &= ~SDHCI_CTRL_HISPD;
 
 	sdhci_write8(sdhci, SDHCI_HOST_CONTROL, reg);
 
@@ -298,15 +298,15 @@ static int at91_sdhci_set_bus_width(struct at91_sdhci *host, unsigned bus_width)
 
 	switch(bus_width) {
 	case MMC_BUS_WIDTH_8:
-		reg |= SDHCI_DATA_WIDTH_8BIT;
+		reg |= SDHCI_CTRL_8BITBUS;
 		break;
 	case MMC_BUS_WIDTH_4:
-		reg &= ~SDHCI_DATA_WIDTH_8BIT;
-		reg |= SDHCI_DATA_WIDTH_4BIT;
+		reg &= ~SDHCI_CTRL_8BITBUS;
+		reg |= SDHCI_CTRL_8BITBUS;
 		break;
 	default:
-		reg &= ~SDHCI_DATA_WIDTH_8BIT;
-		reg &= ~SDHCI_DATA_WIDTH_4BIT;
+		reg &= ~SDHCI_CTRL_8BITBUS;
+		reg &= ~SDHCI_CTRL_8BITBUS;
 	}
 
 	sdhci_write8(sdhci, SDHCI_HOST_CONTROL, reg);
diff --git a/drivers/mci/dove-sdhci.c b/drivers/mci/dove-sdhci.c
index 9c10e67eb8..cafc9dc579 100644
--- a/drivers/mci/dove-sdhci.c
+++ b/drivers/mci/dove-sdhci.c
@@ -224,20 +224,20 @@ static void dove_sdhci_mci_set_ios(struct mci_host *mci, struct mci_ios *ios)
 
 	/* set bus width */
 	val = sdhci_read8(&host->sdhci, SDHCI_HOST_CONTROL) &
-		~(SDHCI_DATA_WIDTH_4BIT | SDHCI_DATA_WIDTH_8BIT);
+		~(SDHCI_CTRL_8BITBUS | SDHCI_CTRL_8BITBUS);
 	switch (ios->bus_width) {
 	case MMC_BUS_WIDTH_8:
-		val |= SDHCI_DATA_WIDTH_8BIT;
+		val |= SDHCI_CTRL_8BITBUS;
 		break;
 	case MMC_BUS_WIDTH_4:
-		val |= SDHCI_DATA_WIDTH_4BIT;
+		val |= SDHCI_CTRL_8BITBUS;
 		break;
 	}
 
 	if (ios->clock > 26000000)
-		val |= SDHCI_HIGHSPEED_EN;
+		val |= SDHCI_CTRL_HISPD;
 	else
-		val &= ~SDHCI_HIGHSPEED_EN;
+		val &= ~SDHCI_CTRL_HISPD;
 
 	sdhci_write8(&host->sdhci, SDHCI_HOST_CONTROL, val);
 
diff --git a/drivers/mci/sdhci.h b/drivers/mci/sdhci.h
index aa6dd9824e..b4de77abe4 100644
--- a/drivers/mci/sdhci.h
+++ b/drivers/mci/sdhci.h
@@ -54,11 +54,18 @@
 #define SDHCI_PRESENT_STATE1					0x26
 #define SDHCI_HOST_CONTROL__POWER_CONTROL__BLOCK_GAP_CONTROL	0x28
 #define SDHCI_HOST_CONTROL					0x28
-#define  SDHCI_CARD_DETECT_SIGNAL_SELECTION	BIT(7)
-#define  SDHCI_CARD_DETECT_TEST_LEVEL		BIT(6)
-#define  SDHCI_DATA_WIDTH_8BIT			BIT(5)
-#define  SDHCI_HIGHSPEED_EN			BIT(2)
-#define  SDHCI_DATA_WIDTH_4BIT			BIT(1)
+#define  SDHCI_CTRL_LED         BIT(0)
+#define  SDHCI_CTRL_4BITBUS     BIT(1)
+#define  SDHCI_CTRL_HISPD       BIT(2)
+#define  SDHCI_CTRL_DMA_MASK    0x18
+#define   SDHCI_CTRL_SDMA       0x00
+#define   SDHCI_CTRL_ADMA1      0x08
+#define   SDHCI_CTRL_ADMA32     0x10
+#define   SDHCI_CTRL_ADMA64     0x18
+#define   SDHCI_CTRL_ADMA3      0x18
+#define  SDHCI_CTRL_8BITBUS     BIT(5)
+#define  SDHCI_CTRL_CDTEST_INS  BIT(6)
+#define  SDHCI_CTRL_CDTEST_EN   BIT(7)
 #define SDHCI_POWER_CONTROL					0x29
 #define  SDHCI_POWER_ON				0x01
 #define  SDHCI_POWER_180			0x0A