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author | Sascha Hauer <s.hauer@pengutronix.de> | 2023-05-11 16:30:44 +0200 |
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committer | Sascha Hauer <s.hauer@pengutronix.de> | 2023-05-22 12:38:17 +0200 |
commit | b53744ffe333db8ee426fe7e5e93eb82a16bd9a9 (patch) | |
tree | 26bb1291d223a4dd56a7bd0ee4b651d91752d0de /drivers | |
parent | 6dba5339fddde7cb6825f0dae648ca20e6d40d18 (diff) | |
download | barebox-b53744ffe333db8ee426fe7e5e93eb82a16bd9a9.tar.gz barebox-b53744ffe333db8ee426fe7e5e93eb82a16bd9a9.tar.xz |
ARM: mmu64: Use two level pagetables in early code
So far we used 1GiB sized sections in the early MMU setup. This has
the disadvantage that we can't use the MMU in early code when we
require a finer granularity. Rockchip for example keeps TF-A code
in the lower memory so the code just skipped MMU initialization.
Also we can't properly map the OP-TEE space at the end of SDRAM non
executable.
With this patch we now use two level page tables and can map with 4KiB
granularity.
The MMU setup in barebox proper changes as well. Instead of disabling
the MMU for reconfiguration we can now keep the MMU enabled and just
add the mappings for SDRAM banks not known to the early code.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'drivers')
0 files changed, 0 insertions, 0 deletions