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authorSascha Hauer <s.hauer@pengutronix.de>2019-03-11 09:31:39 +0100
committerSascha Hauer <s.hauer@pengutronix.de>2019-03-11 10:02:36 +0100
commitdf44d586d0d70c2189103e60807d33f3267e8021 (patch)
tree81cb03b3282ca0e514dc2f75c803f9d51c5fb0fe /drivers
parent9339b5f05484b5e9f4a7e0b08b2c6ca6599aca6d (diff)
downloadbarebox-df44d586d0d70c2189103e60807d33f3267e8021.tar.gz
clk: divider: Support CLK_DIVIDER_READ_ONLY flag
To support a readonly divider add the CLK_DIVIDER_READ_ONLY flag. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'drivers')
-rw-r--r--drivers/clk/clk-divider.c7
-rw-r--r--drivers/clk/rockchip/clk-rk3188.c1
-rw-r--r--drivers/clk/rockchip/clk-rk3288.c1
3 files changed, 7 insertions, 2 deletions
diff --git a/drivers/clk/clk-divider.c b/drivers/clk/clk-divider.c
index 407aae7..d9d3407 100644
--- a/drivers/clk/clk-divider.c
+++ b/drivers/clk/clk-divider.c
@@ -203,8 +203,12 @@ static int clk_divider_bestdiv(struct clk *clk, unsigned long rate,
static long clk_divider_round_rate(struct clk *clk, unsigned long rate,
unsigned long *parent_rate)
{
+ struct clk_divider *divider = container_of(clk, struct clk_divider, clk);
int div;
+ if (divider->flags & CLK_DIVIDER_READ_ONLY)
+ return clk_divider_recalc_rate(clk, *parent_rate);
+
div = clk_divider_bestdiv(clk, rate, parent_rate);
return *parent_rate / div;
@@ -217,6 +221,9 @@ static int clk_divider_set_rate(struct clk *clk, unsigned long rate,
unsigned int div, value;
u32 val;
+ if (divider->flags & CLK_DIVIDER_READ_ONLY)
+ return 0;
+
if (clk->flags & CLK_SET_RATE_PARENT) {
unsigned long best_parent_rate = parent_rate;
div = clk_divider_bestdiv(clk, rate, &best_parent_rate);
diff --git a/drivers/clk/rockchip/clk-rk3188.c b/drivers/clk/rockchip/clk-rk3188.c
index 7dda296..8ed3a6d 100644
--- a/drivers/clk/rockchip/clk-rk3188.c
+++ b/drivers/clk/rockchip/clk-rk3188.c
@@ -26,7 +26,6 @@
#define RK3188_GRF_SOC_STATUS 0xac
#define CLK_SET_RATE_NO_REPARENT 0
-#define CLK_DIVIDER_READ_ONLY 0
enum rk3188_plls {
apll, cpll, dpll, gpll,
diff --git a/drivers/clk/rockchip/clk-rk3288.c b/drivers/clk/rockchip/clk-rk3288.c
index bb111e1..e7cc9c1 100644
--- a/drivers/clk/rockchip/clk-rk3288.c
+++ b/drivers/clk/rockchip/clk-rk3288.c
@@ -26,7 +26,6 @@
#define RK3288_GRF_SOC_STATUS1 0x284
#define CLK_SET_RATE_NO_REPARENT 0
-#define CLK_DIVIDER_READ_ONLY 0
enum rk3288_plls {
apll, dpll, cpll, gpll, npll,