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authorSascha Hauer <s.hauer@pengutronix.de>2019-04-05 14:51:50 +0200
committerSascha Hauer <s.hauer@pengutronix.de>2019-04-08 10:16:55 +0200
commit1dc748b3b202cadf9b799874d9af8d441ee556bc (patch)
tree58fd3c90a40e2d0128b0c7f36d63d7fc126bb20d /dts/Bindings/arm/atmel-sysregs.txt
parent9688b49cd3bc0b61a019e8e1311236c9975a0777 (diff)
downloadbarebox-1dc748b3b202cadf9b799874d9af8d441ee556bc.tar.gz
barebox-1dc748b3b202cadf9b799874d9af8d441ee556bc.tar.xz
dts: update to v5.1-rc1
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'dts/Bindings/arm/atmel-sysregs.txt')
-rw-r--r--dts/Bindings/arm/atmel-sysregs.txt4
1 files changed, 3 insertions, 1 deletions
diff --git a/dts/Bindings/arm/atmel-sysregs.txt b/dts/Bindings/arm/atmel-sysregs.txt
index 14f319f694..e61d00e25b 100644
--- a/dts/Bindings/arm/atmel-sysregs.txt
+++ b/dts/Bindings/arm/atmel-sysregs.txt
@@ -21,7 +21,8 @@ Its subnodes can be:
RSTC Reset Controller required properties:
- compatible: Should be "atmel,<chip>-rstc".
- <chip> can be "at91sam9260" or "at91sam9g45" or "sama5d3"
+ <chip> can be "at91sam9260", "at91sam9g45", "sama5d3" or "samx7"
+ it also can be "microchip,sam9x60-rstc"
- reg: Should contain registers location and length
- clocks: phandle to input clock.
@@ -147,6 +148,7 @@ required properties:
- compatible: Should be "atmel,<chip>-sfr", "syscon" or
"atmel,<chip>-sfrbu", "syscon"
<chip> can be "sama5d3", "sama5d4" or "sama5d2".
+ It also can be "microchip,sam9x60-sfr", "syscon".
- reg: Should contain registers location and length
sfr@f0038000 {