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author | Sascha Hauer <s.hauer@pengutronix.de> | 2014-08-07 06:14:30 +0200 |
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committer | Sascha Hauer <s.hauer@pengutronix.de> | 2014-08-07 06:14:30 +0200 |
commit | e3ff4dfa41b4e8afc26b69e5c3d8c127f0f37c39 (patch) | |
tree | fd2a441a7528003e0876ef0a4209cd7d9e28e7bc /dts/Bindings/arm/exynos/power_domain.txt | |
parent | 8b464dc6eec4d1fd58875451671456393181e980 (diff) | |
parent | e8ee06fe59e468dcd7404b8eed75d78af9c02593 (diff) | |
download | barebox-e3ff4dfa41b4e8afc26b69e5c3d8c127f0f37c39.tar.gz barebox-e3ff4dfa41b4e8afc26b69e5c3d8c127f0f37c39.tar.xz |
Merge branch 'for-next/dts'
Diffstat (limited to 'dts/Bindings/arm/exynos/power_domain.txt')
-rw-r--r-- | dts/Bindings/arm/exynos/power_domain.txt | 20 |
1 files changed, 20 insertions, 0 deletions
diff --git a/dts/Bindings/arm/exynos/power_domain.txt b/dts/Bindings/arm/exynos/power_domain.txt index 5216b41901..8b4f7b7fe8 100644 --- a/dts/Bindings/arm/exynos/power_domain.txt +++ b/dts/Bindings/arm/exynos/power_domain.txt @@ -9,6 +9,18 @@ Required Properties: - reg: physical base address of the controller and length of memory mapped region. +Optional Properties: +- clocks: List of clock handles. The parent clocks of the input clocks to the + devices in this power domain are set to oscclk before power gating + and restored back after powering on a domain. This is required for + all domains which are powered on and off and not required for unused + domains. +- clock-names: The following clocks can be specified: + - oscclk: Oscillator clock. + - pclkN, clkN: Pairs of parent of input clock and input clock to the + devices in this power domain. Maximum of 4 pairs (N = 0 to 3) + are supported currently. + Node of a device using power domains must have a samsung,power-domain property defined with a phandle to respective power domain. @@ -19,6 +31,14 @@ Example: reg = <0x10023C00 0x10>; }; + mfc_pd: power-domain@10044060 { + compatible = "samsung,exynos4210-pd"; + reg = <0x10044060 0x20>; + clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MOUT_SW_ACLK333>, + <&clock CLK_MOUT_USER_ACLK333>; + clock-names = "oscclk", "pclk0", "clk0"; + }; + Example of the node using power domain: node { |