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author | Sascha Hauer <s.hauer@pengutronix.de> | 2017-01-10 08:26:15 +0100 |
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committer | Sascha Hauer <s.hauer@pengutronix.de> | 2017-01-10 08:48:45 +0100 |
commit | a40531fb3c11dc4ee8cca43c91b471da1fd3c1ab (patch) | |
tree | 35f886d87a77df7bac8a587a04647691db541a2e /dts/Bindings/arm/fsl.txt | |
parent | 81462901ce3d677ce318150f7027e2ce1cf97c41 (diff) | |
download | barebox-a40531fb3c11dc4ee8cca43c91b471da1fd3c1ab.tar.gz barebox-a40531fb3c11dc4ee8cca43c91b471da1fd3c1ab.tar.xz |
dts: update to v4.10-rc1
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'dts/Bindings/arm/fsl.txt')
-rw-r--r-- | dts/Bindings/arm/fsl.txt | 34 |
1 files changed, 31 insertions, 3 deletions
diff --git a/dts/Bindings/arm/fsl.txt b/dts/Bindings/arm/fsl.txt index dbbc095202..d6ee9c6e1d 100644 --- a/dts/Bindings/arm/fsl.txt +++ b/dts/Bindings/arm/fsl.txt @@ -97,7 +97,7 @@ Freescale LS1021A Platform Device Tree Bindings Required root node compatible properties: - compatible = "fsl,ls1021a"; -Freescale LS1021A SoC-specific Device Tree Bindings +Freescale SoC-specific Device Tree Bindings ------------------------------------------- Freescale SCFG @@ -105,7 +105,11 @@ Freescale SCFG configuration and status registers for the chip. Such as getting PEX port status. Required properties: - - compatible: should be "fsl,ls1021a-scfg" + - compatible: Should contain a chip-specific compatible string, + Chip-specific strings are of the form "fsl,<chip>-scfg", + The following <chip>s are known to be supported: + ls1021a, ls1043a, ls1046a, ls2080a. + - reg: should contain base address and length of SCFG memory-mapped registers Example: @@ -119,7 +123,11 @@ Freescale DCFG configuration and status for the device. Such as setting the secondary core start address and release the secondary core from holdoff and startup. Required properties: - - compatible: should be "fsl,ls1021a-dcfg" + - compatible: Should contain a chip-specific compatible string, + Chip-specific strings are of the form "fsl,<chip>-dcfg", + The following <chip>s are known to be supported: + ls1021a, ls1043a, ls1046a, ls2080a. + - reg : should contain base address and length of DCFG memory-mapped registers Example: @@ -131,6 +139,10 @@ Example: Freescale ARMv8 based Layerscape SoC family Device Tree Bindings ---------------------------------------------------------------- +LS1043A SoC +Required root node properties: + - compatible = "fsl,ls1043a"; + LS1043A ARMv8 based RDB Board Required root node properties: - compatible = "fsl,ls1043a-rdb", "fsl,ls1043a"; @@ -139,6 +151,22 @@ LS1043A ARMv8 based QDS Board Required root node properties: - compatible = "fsl,ls1043a-qds", "fsl,ls1043a"; +LS1046A SoC +Required root node properties: + - compatible = "fsl,ls1046a"; + +LS1046A ARMv8 based QDS Board +Required root node properties: + - compatible = "fsl,ls1046a-qds", "fsl,ls1046a"; + +LS1046A ARMv8 based RDB Board +Required root node properties: + - compatible = "fsl,ls1046a-rdb", "fsl,ls1046a"; + +LS2080A SoC +Required root node properties: + - compatible = "fsl,ls2080a"; + LS2080A ARMv8 based Simulator model Required root node properties: - compatible = "fsl,ls2080a-simu", "fsl,ls2080a"; |