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author | Sascha Hauer <s.hauer@pengutronix.de> | 2014-10-21 13:11:04 +0200 |
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committer | Sascha Hauer <s.hauer@pengutronix.de> | 2014-10-21 13:11:04 +0200 |
commit | 604ad71929a1deabe77b7ab9c3655d82002d79c9 (patch) | |
tree | 8640b00b7d9945560f3b31dd3efd947f08d0d319 /dts/Bindings/arm/l2cc.txt | |
parent | 826d399c448b4e08d73731448d0400c449e9fc58 (diff) | |
download | barebox-604ad71929a1deabe77b7ab9c3655d82002d79c9.tar.gz barebox-604ad71929a1deabe77b7ab9c3655d82002d79c9.tar.xz |
dts: update to v3.18-rc1
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'dts/Bindings/arm/l2cc.txt')
-rw-r--r-- | dts/Bindings/arm/l2cc.txt | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/dts/Bindings/arm/l2cc.txt b/dts/Bindings/arm/l2cc.txt index af527ee111..292ef7ca30 100644 --- a/dts/Bindings/arm/l2cc.txt +++ b/dts/Bindings/arm/l2cc.txt @@ -2,6 +2,10 @@ ARM cores often have a separate level 2 cache controller. There are various implementations of the L2 cache controller with compatible programming models. +Some of the properties that are just prefixed "cache-*" are taken from section +3.7.3 of the ePAPR v1.1 specification which can be found at: +https://www.power.org/wp-content/uploads/2012/06/Power_ePAPR_APPROVED_v1.1.pdf + The ARM L2 cache representation in the device tree should be done as follows: Required properties: @@ -44,6 +48,12 @@ Optional properties: I/O coherent mode. Valid only when the arm,pl310-cache compatible string is used. - interrupts : 1 combined interrupt. +- cache-size : specifies the size in bytes of the cache +- cache-sets : specifies the number of associativity sets of the cache +- cache-block-size : specifies the size in bytes of a cache block +- cache-line-size : specifies the size in bytes of a line in the cache, + if this is not specified, the line size is assumed to be equal to the + cache block size - cache-id-part: cache id part number to be used if it is not present on hardware - wt-override: If present then L2 is forced to Write through mode |