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author | Ahmad Fatoum <a.fatoum@pengutronix.de> | 2022-06-23 15:07:16 +0200 |
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committer | Sascha Hauer <s.hauer@pengutronix.de> | 2022-06-27 08:44:36 +0200 |
commit | 3e98eb88e3f99c9a5c71bcd934134decc8ccc2a8 (patch) | |
tree | b4987fd4dbb52117d214ffb112241f2504987e76 /dts/Bindings/arm/sprd | |
parent | 2a4a08d89f9109bfac4e2d8dcae0048265d11a28 (diff) | |
download | barebox-3e98eb88e3f99c9a5c71bcd934134decc8ccc2a8.tar.gz barebox-3e98eb88e3f99c9a5c71bcd934134decc8ccc2a8.tar.xz |
ARM: i.MX8MQ: initialize ADDRMAP7
Older NXP DDR spreadsheets don't initialize ADDRMAP7, leaving it at its
POR default of zero. Now that barebox looks at ADDRMAP7 to be able to
correctly detect bigger memory sizes, barebox proper on boards with
older spreadsheets may read back 4x times as much RAM as actually
fitted.
MNT Reform LPDDR4 setup already writes 0xf0f (the neutral ignore-me
value for the register) into ADDRMAP7. Follow suit for the other
i.MX8MQ boards that don't. In-tree Non-i.MX8MQ boards aren't affected.
Out of tree boards might and will get a common workaround in a follow-up
commit. No workaround for out of tree i.MX8MQ boards.
Tested on i.MX8M-EVK (i.MX8MQuad), where now 3G are correctly detected
instead of 12G.
Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Link: https://lore.barebox.org/20220623130717.1447999-5-a.fatoum@pengutronix.de
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'dts/Bindings/arm/sprd')
0 files changed, 0 insertions, 0 deletions