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| author | Sascha Hauer <s.hauer@pengutronix.de> | 2015-02-09 08:45:25 +0100 |
|---|---|---|
| committer | Sascha Hauer <s.hauer@pengutronix.de> | 2015-02-11 09:50:08 +0100 |
| commit | ab001302c8e1718110bb8839c270d2caa817b214 (patch) | |
| tree | f5ab4feb5242e548917c3536b8510080df9a4e8f /dts/Bindings/bus/brcm,gisb-arb.txt | |
| parent | c937ef5d34ede89ae382cfe6d98ba366859a65af (diff) | |
| download | barebox-ab001302c8e1718110bb8839c270d2caa817b214.tar.gz barebox-ab001302c8e1718110bb8839c270d2caa817b214.tar.xz | |
dts: update to v3.19-rc1
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'dts/Bindings/bus/brcm,gisb-arb.txt')
| -rw-r--r-- | dts/Bindings/bus/brcm,gisb-arb.txt | 6 |
1 files changed, 5 insertions, 1 deletions
diff --git a/dts/Bindings/bus/brcm,gisb-arb.txt b/dts/Bindings/bus/brcm,gisb-arb.txt index e2d501d20c..1eceefb20f 100644 --- a/dts/Bindings/bus/brcm,gisb-arb.txt +++ b/dts/Bindings/bus/brcm,gisb-arb.txt @@ -2,7 +2,11 @@ Broadcom GISB bus Arbiter controller Required properties: -- compatible: should be "brcm,gisb-arb" +- compatible: + "brcm,gisb-arb" or "brcm,bcm7445-gisb-arb" for 28nm chips + "brcm,bcm7435-gisb-arb" for newer 40nm chips + "brcm,bcm7400-gisb-arb" for older 40nm chips and all 65nm chips + "brcm,bcm7038-gisb-arb" for 130nm chips - reg: specifies the base physical address and size of the registers - interrupt-parent: specifies the phandle to the parent interrupt controller this arbiter gets interrupt line from |