dts: update to v4.6-rc1

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

1 files changed, 4 insertions, 1 deletions

diff --git a/dts/Bindings/clock/axi-clkgen.txt b/dts/Bindings/clock/axi-clkgen.txt
index 20e1704e7d..fb40da303d 100644
--- a/dts/Bindings/clock/axi-clkgen.txt
+++ b/dts/Bindings/clock/axi-clkgen.txt
@@ -8,7 +8,10 @@ Required properties:
 - compatible : shall be "adi,axi-clkgen-1.00.a" or "adi,axi-clkgen-2.00.a".
 - #clock-cells : from common clock binding; Should always be set to 0.
 - reg : Address and length of the axi-clkgen register set.
-- clocks : Phandle and clock specifier for the parent clock.
+- clocks : Phandle and clock specifier for the parent clock(s). This must
+	either reference one clock if only the first clock input is connected or two
+	if both clock inputs are connected. For the later case the clock connected
+	to the first input must be specified first.
 
 Optional properties:
 - clock-output-names : From common clock binding.