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| author | Sascha Hauer <s.hauer@pengutronix.de> | 2017-11-28 11:02:14 +0100 |
|---|---|---|
| committer | Sascha Hauer <s.hauer@pengutronix.de> | 2017-11-28 11:06:44 +0100 |
| commit | 2e9cce8fb1f577088e2b20ae2f461130e13ad190 (patch) | |
| tree | f82ae53e88d36e07608be1b3159da296ed025ef1 /dts/Bindings/clock/renesas,rz-cpg-clocks.txt | |
| parent | c68d466d263827692aa809e6b34abb90a1cab515 (diff) | |
| download | barebox-2e9cce8fb1f577088e2b20ae2f461130e13ad190.tar.gz barebox-2e9cce8fb1f577088e2b20ae2f461130e13ad190.tar.xz | |
dts: update to v4.15-rc1
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'dts/Bindings/clock/renesas,rz-cpg-clocks.txt')
| -rw-r--r-- | dts/Bindings/clock/renesas,rz-cpg-clocks.txt | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/dts/Bindings/clock/renesas,rz-cpg-clocks.txt b/dts/Bindings/clock/renesas,rz-cpg-clocks.txt index bb5d942075..8ff3e2774e 100644 --- a/dts/Bindings/clock/renesas,rz-cpg-clocks.txt +++ b/dts/Bindings/clock/renesas,rz-cpg-clocks.txt @@ -1,6 +1,6 @@ -* Renesas RZ Clock Pulse Generator (CPG) +* Renesas RZ/A1 Clock Pulse Generator (CPG) -The CPG generates core clocks for the RZ SoCs. It includes the PLL, variable +The CPG generates core clocks for the RZ/A1 SoCs. It includes the PLL, variable CPU and GPU clocks, and several fixed ratio dividers. The CPG also provides a Clock Domain for SoC devices, in combination with the CPG Module Stop (MSTP) Clocks. |