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| author | Sascha Hauer <s.hauer@pengutronix.de> | 2014-06-17 22:16:07 +0200 |
|---|---|---|
| committer | Sascha Hauer <s.hauer@pengutronix.de> | 2014-06-19 09:41:51 +0200 |
| commit | 9313920df6d3d55fbd03ce8ec1c0da9a10c29824 (patch) | |
| tree | ef80d80abbaf46293b777ead52caddd9d5d97644 /dts/Bindings/clock/ti/dpll.txt | |
| parent | 83e875e1f45beffe399cff0ff6128e0fca9da168 (diff) | |
| download | barebox-9313920df6d3d55fbd03ce8ec1c0da9a10c29824.tar.gz barebox-9313920df6d3d55fbd03ce8ec1c0da9a10c29824.tar.xz | |
dts: update to v3.16-rc1
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'dts/Bindings/clock/ti/dpll.txt')
| -rw-r--r-- | dts/Bindings/clock/ti/dpll.txt | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/dts/Bindings/clock/ti/dpll.txt b/dts/Bindings/clock/ti/dpll.txt index 30bfdb7c9f..df57009ff8 100644 --- a/dts/Bindings/clock/ti/dpll.txt +++ b/dts/Bindings/clock/ti/dpll.txt @@ -24,12 +24,14 @@ Required properties: "ti,omap4-dpll-core-clock", "ti,omap4-dpll-m4xen-clock", "ti,omap4-dpll-j-type-clock", + "ti,omap5-mpu-dpll-clock", "ti,am3-dpll-no-gate-clock", "ti,am3-dpll-j-type-clock", "ti,am3-dpll-no-gate-j-type-clock", "ti,am3-dpll-clock", "ti,am3-dpll-core-clock", "ti,am3-dpll-x2-clock", + "ti,omap2-dpll-core-clock", - #clock-cells : from common clock binding; shall be set to 0. - clocks : link phandles of parent clocks, first entry lists reference clock @@ -41,6 +43,7 @@ Required properties: "mult-div1" - contains the multiplier / divider register base address "autoidle" - contains the autoidle register base address (optional) ti,am3-* dpll types do not have autoidle register + ti,omap2-* dpll type does not support idlest / autoidle registers Optional properties: - DPLL mode setting - defining any one or more of the following overrides @@ -73,3 +76,10 @@ Examples: clocks = <&sys_clkin_ck>, <&sys_clkin_ck>; reg = <0x90>, <0x5c>, <0x68>; }; + + dpll_ck: dpll_ck { + #clock-cells = <0>; + compatible = "ti,omap2-dpll-core-clock"; + clocks = <&sys_ck>, <&sys_ck>; + reg = <0x0500>, <0x0540>; + }; |