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author | Sascha Hauer <s.hauer@pengutronix.de> | 2016-02-03 10:25:36 +0100 |
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committer | Sascha Hauer <s.hauer@pengutronix.de> | 2016-02-04 08:40:36 +0100 |
commit | 0ff58575c9d66f660886387c2e68d8c5c724e87b (patch) | |
tree | 4a889d1478da83ae46db96f5c049872cdb90eeb6 /dts/Bindings/display/msm/mdp.txt | |
parent | a0da52f83c36a81984e0fca4b75d522b955df267 (diff) | |
download | barebox-0ff58575c9d66f660886387c2e68d8c5c724e87b.tar.gz barebox-0ff58575c9d66f660886387c2e68d8c5c724e87b.tar.xz |
dts: update to v4.5-rc1
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'dts/Bindings/display/msm/mdp.txt')
-rw-r--r-- | dts/Bindings/display/msm/mdp.txt | 26 |
1 files changed, 18 insertions, 8 deletions
diff --git a/dts/Bindings/display/msm/mdp.txt b/dts/Bindings/display/msm/mdp.txt index 0833edaba4..a214f6cd03 100644 --- a/dts/Bindings/display/msm/mdp.txt +++ b/dts/Bindings/display/msm/mdp.txt @@ -2,18 +2,28 @@ Qualcomm adreno/snapdragon display controller Required properties: - compatible: - * "qcom,mdp" - mdp4 + * "qcom,mdp4" - mdp4 + * "qcom,mdp5" - mdp5 - reg: Physical base address and length of the controller's registers. - interrupts: The interrupt signal from the display controller. - connectors: array of phandles for output device(s) - clocks: device clocks See ../clocks/clock-bindings.txt for details. -- clock-names: the following clocks are required: - * "core_clk" - * "iface_clk" - * "src_clk" - * "hdmi_clk" - * "mpd_clk" +- clock-names: the following clocks are required. + For MDP4: + * "core_clk" + * "iface_clk" + * "lut_clk" + * "src_clk" + * "hdmi_clk" + * "mdp_clk" + For MDP5: + * "bus_clk" + * "iface_clk" + * "core_clk_src" + * "core_clk" + * "lut_clk" (some MDP5 versions may not need this) + * "vsync_clk" Optional properties: - gpus: phandle for gpu device @@ -26,7 +36,7 @@ Example: ... mdp: qcom,mdp@5100000 { - compatible = "qcom,mdp"; + compatible = "qcom,mdp4"; reg = <0x05100000 0xf0000>; interrupts = <GIC_SPI 75 0>; connectors = <&hdmi>; |