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author | Sascha Hauer <s.hauer@pengutronix.de> | 2020-06-23 12:14:59 +0200 |
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committer | Sascha Hauer <s.hauer@pengutronix.de> | 2020-07-05 20:49:06 +0200 |
commit | abef60363d8ecac66e45853f328afa8eeb9e00fd (patch) | |
tree | c7d6f1dcf0ef5154b9182da86f1acad048cb7da1 /dts/Bindings/dma | |
parent | e307bc559a2830b7f695150212ea1b26cdca69fb (diff) | |
download | barebox-abef60363d8ecac66e45853f328afa8eeb9e00fd.tar.gz barebox-abef60363d8ecac66e45853f328afa8eeb9e00fd.tar.xz |
dts: update to v5.8-rc1
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'dts/Bindings/dma')
-rw-r--r-- | dts/Bindings/dma/dma-common.yaml | 3 | ||||
-rw-r--r-- | dts/Bindings/dma/ingenic,dma.yaml | 80 | ||||
-rw-r--r-- | dts/Bindings/dma/jz4780-dma.txt | 64 | ||||
-rw-r--r-- | dts/Bindings/dma/mtk-uart-apdma.txt | 3 | ||||
-rw-r--r-- | dts/Bindings/dma/renesas,rcar-dmac.txt | 117 | ||||
-rw-r--r-- | dts/Bindings/dma/renesas,rcar-dmac.yaml | 150 | ||||
-rw-r--r-- | dts/Bindings/dma/renesas,usb-dmac.txt | 55 | ||||
-rw-r--r-- | dts/Bindings/dma/renesas,usb-dmac.yaml | 102 | ||||
-rw-r--r-- | dts/Bindings/dma/sifive,fu540-c000-pdma.yaml | 2 | ||||
-rw-r--r-- | dts/Bindings/dma/st,stm32-dma.yaml | 5 | ||||
-rw-r--r-- | dts/Bindings/dma/ti/k3-udma.yaml | 29 |
11 files changed, 352 insertions, 258 deletions
diff --git a/dts/Bindings/dma/dma-common.yaml b/dts/Bindings/dma/dma-common.yaml index 02a34ba2b4..c365926833 100644 --- a/dts/Bindings/dma/dma-common.yaml +++ b/dts/Bindings/dma/dma-common.yaml @@ -31,8 +31,7 @@ properties: kernel. i.e. first channel corresponds to LSB. The first item in the array is for channels 0-31, the second is for channels 32-63, etc. - allOf: - - $ref: /schemas/types.yaml#/definitions/uint32-array + $ref: /schemas/types.yaml#/definitions/uint32-array items: minItems: 1 # Should be enough diff --git a/dts/Bindings/dma/ingenic,dma.yaml b/dts/Bindings/dma/ingenic,dma.yaml new file mode 100644 index 0000000000..92794c5005 --- /dev/null +++ b/dts/Bindings/dma/ingenic,dma.yaml @@ -0,0 +1,80 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/dma/ingenic,dma.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Ingenic SoCs DMA Controller DT bindings + +maintainers: + - Paul Cercueil <paul@crapouillou.net> + +allOf: + - $ref: "dma-controller.yaml#" + +properties: + compatible: + enum: + - ingenic,jz4740-dma + - ingenic,jz4725b-dma + - ingenic,jz4770-dma + - ingenic,jz4780-dma + - ingenic,x1000-dma + - ingenic,x1830-dma + + reg: + items: + - description: Channel-specific registers + - description: System control registers + + interrupts: + maxItems: 1 + + clocks: + maxItems: 1 + + "#dma-cells": + const: 2 + description: > + DMA clients must use the format described in dma.txt, giving a phandle + to the DMA controller plus the following 2 integer cells: + + - Request type: The DMA request type for transfers to/from the + device on the allocated channel, as defined in the SoC documentation. + + - Channel: If set to 0xffffffff, any available channel will be allocated + for the client. Otherwise, the exact channel specified will be used. + The channel should be reserved on the DMA controller using the + ingenic,reserved-channels property. + + ingenic,reserved-channels: + $ref: /schemas/types.yaml#definitions/uint32 + description: > + Bitmask of channels to reserve for devices that need a specific + channel. These channels will only be assigned when explicitely + requested by a client. The primary use for this is channels 0 and + 1, which can be configured to have special behaviour for NAND/BCH + when using programmable firmware. + +required: + - compatible + - reg + - interrupts + - clocks + +examples: + - | + #include <dt-bindings/clock/jz4780-cgu.h> + dma: dma-controller@13420000 { + compatible = "ingenic,jz4780-dma"; + reg = <0x13420000 0x400>, <0x13421000 0x40>; + + interrupt-parent = <&intc>; + interrupts = <10>; + + clocks = <&cgu JZ4780_CLK_PDMA>; + + #dma-cells = <2>; + + ingenic,reserved-channels = <0x3>; + }; diff --git a/dts/Bindings/dma/jz4780-dma.txt b/dts/Bindings/dma/jz4780-dma.txt deleted file mode 100644 index 3459e77be2..0000000000 --- a/dts/Bindings/dma/jz4780-dma.txt +++ /dev/null @@ -1,64 +0,0 @@ -* Ingenic XBurst DMA Controller - -Required properties: - -- compatible: Should be one of: - * ingenic,jz4740-dma - * ingenic,jz4725b-dma - * ingenic,jz4770-dma - * ingenic,jz4780-dma - * ingenic,x1000-dma - * ingenic,x1830-dma -- reg: Should contain the DMA channel registers location and length, followed - by the DMA controller registers location and length. -- interrupts: Should contain the interrupt specifier of the DMA controller. -- clocks: Should contain a clock specifier for the JZ4780/X1000/X1830 PDMA - clock. -- #dma-cells: Must be <2>. Number of integer cells in the dmas property of - DMA clients (see below). - -Optional properties: - -- ingenic,reserved-channels: Bitmask of channels to reserve for devices that - need a specific channel. These channels will only be assigned when explicitly - requested by a client. The primary use for this is channels 0 and 1, which - can be configured to have special behaviour for NAND/BCH when using - programmable firmware. - -Example: - -dma: dma-controller@13420000 { - compatible = "ingenic,jz4780-dma"; - reg = <0x13420000 0x400 - 0x13421000 0x40>; - - interrupt-parent = <&intc>; - interrupts = <10>; - - clocks = <&cgu JZ4780_CLK_PDMA>; - - #dma-cells = <2>; - - ingenic,reserved-channels = <0x3>; -}; - -DMA clients must use the format described in dma.txt, giving a phandle to the -DMA controller plus the following 2 integer cells: - -1. Request type: The DMA request type for transfers to/from the device on - the allocated channel, as defined in the SoC documentation. - -2. Channel: If set to 0xffffffff, any available channel will be allocated for - the client. Otherwise, the exact channel specified will be used. The channel - should be reserved on the DMA controller using the ingenic,reserved-channels - property. - -Example: - -uart0: serial@10030000 { - ... - dmas = <&dma 0x14 0xffffffff - &dma 0x15 0xffffffff>; - dma-names = "tx", "rx"; - ... -}; diff --git a/dts/Bindings/dma/mtk-uart-apdma.txt b/dts/Bindings/dma/mtk-uart-apdma.txt index 5d6f98c43e..2117db0ce4 100644 --- a/dts/Bindings/dma/mtk-uart-apdma.txt +++ b/dts/Bindings/dma/mtk-uart-apdma.txt @@ -21,7 +21,8 @@ Required properties: Examples: apdma: dma-controller@11000400 { - compatible = "mediatek,mt2712-uart-dma"; + compatible = "mediatek,mt2712-uart-dma", + "mediatek,mt6577-uart-dma"; reg = <0 0x11000400 0 0x80>, <0 0x11000480 0 0x80>, <0 0x11000500 0 0x80>, diff --git a/dts/Bindings/dma/renesas,rcar-dmac.txt b/dts/Bindings/dma/renesas,rcar-dmac.txt deleted file mode 100644 index b7f81c63be..0000000000 --- a/dts/Bindings/dma/renesas,rcar-dmac.txt +++ /dev/null @@ -1,117 +0,0 @@ -* Renesas R-Car (RZ/G) DMA Controller Device Tree bindings - -Renesas R-Car (Gen 2/3) and RZ/G SoCs have multiple multi-channel DMA -controller instances named DMAC capable of serving multiple clients. Channels -can be dedicated to specific clients or shared between a large number of -clients. - -Each DMA client is connected to one dedicated port of the DMAC, identified by -an 8-bit port number called the MID/RID. A DMA controller can thus serve up to -256 clients in total. When the number of hardware channels is lower than the -number of clients to be served, channels must be shared between multiple DMA -clients. The association of DMA clients to DMAC channels is fully dynamic and -not described in these device tree bindings. - -Required Properties: - -- compatible: "renesas,dmac-<soctype>", "renesas,rcar-dmac" as fallback. - Examples with soctypes are: - - "renesas,dmac-r8a7743" (RZ/G1M) - - "renesas,dmac-r8a7744" (RZ/G1N) - - "renesas,dmac-r8a7745" (RZ/G1E) - - "renesas,dmac-r8a77470" (RZ/G1C) - - "renesas,dmac-r8a774a1" (RZ/G2M) - - "renesas,dmac-r8a774b1" (RZ/G2N) - - "renesas,dmac-r8a774c0" (RZ/G2E) - - "renesas,dmac-r8a7790" (R-Car H2) - - "renesas,dmac-r8a7791" (R-Car M2-W) - - "renesas,dmac-r8a7792" (R-Car V2H) - - "renesas,dmac-r8a7793" (R-Car M2-N) - - "renesas,dmac-r8a7794" (R-Car E2) - - "renesas,dmac-r8a7795" (R-Car H3) - - "renesas,dmac-r8a7796" (R-Car M3-W) - - "renesas,dmac-r8a77961" (R-Car M3-W+) - - "renesas,dmac-r8a77965" (R-Car M3-N) - - "renesas,dmac-r8a77970" (R-Car V3M) - - "renesas,dmac-r8a77980" (R-Car V3H) - - "renesas,dmac-r8a77990" (R-Car E3) - - "renesas,dmac-r8a77995" (R-Car D3) - -- reg: base address and length of the registers block for the DMAC - -- interrupts: interrupt specifiers for the DMAC, one for each entry in - interrupt-names. -- interrupt-names: one entry for the error interrupt, named "error", plus one - entry per channel, named "ch%u", where %u is the channel number ranging from - zero to the number of channels minus one. - -- clock-names: "fck" for the functional clock -- clocks: a list of phandle + clock-specifier pairs, one for each entry - in clock-names. -- clock-names: must contain "fck" for the functional clock. - -- #dma-cells: must be <1>, the cell specifies the MID/RID of the DMAC port - connected to the DMA client -- dma-channels: number of DMA channels - -Example: R8A7790 (R-Car H2) SYS-DMACs - - dmac0: dma-controller@e6700000 { - compatible = "renesas,dmac-r8a7790", "renesas,rcar-dmac"; - reg = <0 0xe6700000 0 0x20000>; - interrupts = <0 197 IRQ_TYPE_LEVEL_HIGH - 0 200 IRQ_TYPE_LEVEL_HIGH - 0 201 IRQ_TYPE_LEVEL_HIGH - 0 202 IRQ_TYPE_LEVEL_HIGH - 0 203 IRQ_TYPE_LEVEL_HIGH - 0 204 IRQ_TYPE_LEVEL_HIGH - 0 205 IRQ_TYPE_LEVEL_HIGH - 0 206 IRQ_TYPE_LEVEL_HIGH - 0 207 IRQ_TYPE_LEVEL_HIGH - 0 208 IRQ_TYPE_LEVEL_HIGH - 0 209 IRQ_TYPE_LEVEL_HIGH - 0 210 IRQ_TYPE_LEVEL_HIGH - 0 211 IRQ_TYPE_LEVEL_HIGH - 0 212 IRQ_TYPE_LEVEL_HIGH - 0 213 IRQ_TYPE_LEVEL_HIGH - 0 214 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "error", - "ch0", "ch1", "ch2", "ch3", - "ch4", "ch5", "ch6", "ch7", - "ch8", "ch9", "ch10", "ch11", - "ch12", "ch13", "ch14"; - clocks = <&mstp2_clks R8A7790_CLK_SYS_DMAC0>; - clock-names = "fck"; - #dma-cells = <1>; - dma-channels = <15>; - }; - - dmac1: dma-controller@e6720000 { - compatible = "renesas,dmac-r8a7790", "renesas,rcar-dmac"; - reg = <0 0xe6720000 0 0x20000>; - interrupts = <0 220 IRQ_TYPE_LEVEL_HIGH - 0 216 IRQ_TYPE_LEVEL_HIGH - 0 217 IRQ_TYPE_LEVEL_HIGH - 0 218 IRQ_TYPE_LEVEL_HIGH - 0 219 IRQ_TYPE_LEVEL_HIGH - 0 308 IRQ_TYPE_LEVEL_HIGH - 0 309 IRQ_TYPE_LEVEL_HIGH - 0 310 IRQ_TYPE_LEVEL_HIGH - 0 311 IRQ_TYPE_LEVEL_HIGH - 0 312 IRQ_TYPE_LEVEL_HIGH - 0 313 IRQ_TYPE_LEVEL_HIGH - 0 314 IRQ_TYPE_LEVEL_HIGH - 0 315 IRQ_TYPE_LEVEL_HIGH - 0 316 IRQ_TYPE_LEVEL_HIGH - 0 317 IRQ_TYPE_LEVEL_HIGH - 0 318 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "error", - "ch0", "ch1", "ch2", "ch3", - "ch4", "ch5", "ch6", "ch7", - "ch8", "ch9", "ch10", "ch11", - "ch12", "ch13", "ch14"; - clocks = <&mstp2_clks R8A7790_CLK_SYS_DMAC1>; - clock-names = "fck"; - #dma-cells = <1>; - dma-channels = <15>; - }; diff --git a/dts/Bindings/dma/renesas,rcar-dmac.yaml b/dts/Bindings/dma/renesas,rcar-dmac.yaml new file mode 100644 index 0000000000..b842dfd96a --- /dev/null +++ b/dts/Bindings/dma/renesas,rcar-dmac.yaml @@ -0,0 +1,150 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/dma/renesas,rcar-dmac.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Renesas R-Car and RZ/G DMA Controller + +maintainers: + - Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> + +allOf: + - $ref: "dma-controller.yaml#" + +properties: + compatible: + items: + - enum: + - renesas,dmac-r8a7743 # RZ/G1M + - renesas,dmac-r8a7744 # RZ/G1N + - renesas,dmac-r8a7745 # RZ/G1E + - renesas,dmac-r8a77470 # RZ/G1C + - renesas,dmac-r8a774a1 # RZ/G2M + - renesas,dmac-r8a774b1 # RZ/G2N + - renesas,dmac-r8a774c0 # RZ/G2E + - renesas,dmac-r8a7790 # R-Car H2 + - renesas,dmac-r8a7791 # R-Car M2-W + - renesas,dmac-r8a7792 # R-Car V2H + - renesas,dmac-r8a7793 # R-Car M2-N + - renesas,dmac-r8a7794 # R-Car E2 + - renesas,dmac-r8a7795 # R-Car H3 + - renesas,dmac-r8a7796 # R-Car M3-W + - renesas,dmac-r8a77961 # R-Car M3-W+ + - renesas,dmac-r8a77965 # R-Car M3-N + - renesas,dmac-r8a77970 # R-Car V3M + - renesas,dmac-r8a77980 # R-Car V3H + - renesas,dmac-r8a77990 # R-Car E3 + - renesas,dmac-r8a77995 # R-Car D3 + - const: renesas,rcar-dmac + + reg: + maxItems: 1 + + interrupts: + minItems: 9 + maxItems: 17 + + interrupt-names: + minItems: 9 + maxItems: 17 + items: + - const: error + - pattern: "^ch([0-9]|1[0-5])$" + - pattern: "^ch([0-9]|1[0-5])$" + - pattern: "^ch([0-9]|1[0-5])$" + - pattern: "^ch([0-9]|1[0-5])$" + - pattern: "^ch([0-9]|1[0-5])$" + - pattern: "^ch([0-9]|1[0-5])$" + - pattern: "^ch([0-9]|1[0-5])$" + - pattern: "^ch([0-9]|1[0-5])$" + - pattern: "^ch([0-9]|1[0-5])$" + - pattern: "^ch([0-9]|1[0-5])$" + - pattern: "^ch([0-9]|1[0-5])$" + - pattern: "^ch([0-9]|1[0-5])$" + - pattern: "^ch([0-9]|1[0-5])$" + - pattern: "^ch([0-9]|1[0-5])$" + - pattern: "^ch([0-9]|1[0-5])$" + - pattern: "^ch([0-9]|1[0-5])$" + + clocks: + maxItems: 1 + + clock-names: + maxItems: 1 + items: + - const: fck + + '#dma-cells': + const: 1 + description: + The cell specifies the MID/RID of the DMAC port connected to + the DMA client. + + dma-channels: + minimum: 8 + maximum: 16 + + dma-channel-mask: true + + iommus: + minItems: 8 + maxItems: 16 + + power-domains: + maxItems: 1 + + resets: + maxItems: 1 + +required: + - compatible + - reg + - interrupts + - interrupt-names + - clocks + - clock-names + - '#dma-cells' + - dma-channels + - power-domains + - resets + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/r8a7790-cpg-mssr.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/power/r8a7790-sysc.h> + + dmac0: dma-controller@e6700000 { + compatible = "renesas,dmac-r8a7790", "renesas,rcar-dmac"; + reg = <0xe6700000 0x20000>; + interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "error", + "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7", + "ch8", "ch9", "ch10", "ch11", + "ch12", "ch13", "ch14"; + clocks = <&cpg CPG_MOD 219>; + clock-names = "fck"; + power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 219>; + #dma-cells = <1>; + dma-channels = <15>; + }; diff --git a/dts/Bindings/dma/renesas,usb-dmac.txt b/dts/Bindings/dma/renesas,usb-dmac.txt deleted file mode 100644 index e8f6c42e80..0000000000 --- a/dts/Bindings/dma/renesas,usb-dmac.txt +++ /dev/null @@ -1,55 +0,0 @@ -* Renesas USB DMA Controller Device Tree bindings - -Required Properties: --compatible: "renesas,<soctype>-usb-dmac", "renesas,usb-dmac" as fallback. - Examples with soctypes are: - - "renesas,r8a7743-usb-dmac" (RZ/G1M) - - "renesas,r8a7744-usb-dmac" (RZ/G1N) - - "renesas,r8a7745-usb-dmac" (RZ/G1E) - - "renesas,r8a77470-usb-dmac" (RZ/G1C) - - "renesas,r8a774a1-usb-dmac" (RZ/G2M) - - "renesas,r8a774b1-usb-dmac" (RZ/G2N) - - "renesas,r8a774c0-usb-dmac" (RZ/G2E) - - "renesas,r8a7790-usb-dmac" (R-Car H2) - - "renesas,r8a7791-usb-dmac" (R-Car M2-W) - - "renesas,r8a7793-usb-dmac" (R-Car M2-N) - - "renesas,r8a7794-usb-dmac" (R-Car E2) - - "renesas,r8a7795-usb-dmac" (R-Car H3) - - "renesas,r8a7796-usb-dmac" (R-Car M3-W) - - "renesas,r8a77961-usb-dmac" (R-Car M3-W+) - - "renesas,r8a77965-usb-dmac" (R-Car M3-N) - - "renesas,r8a77990-usb-dmac" (R-Car E3) - - "renesas,r8a77995-usb-dmac" (R-Car D3) -- reg: base address and length of the registers block for the DMAC -- interrupts: interrupt specifiers for the DMAC, one for each entry in - interrupt-names. -- interrupt-names: one entry per channel, named "ch%u", where %u is the - channel number ranging from zero to the number of channels minus one. -- clocks: a list of phandle + clock-specifier pairs. -- #dma-cells: must be <1>, the cell specifies the channel number of the DMAC - port connected to the DMA client. -- dma-channels: number of DMA channels - -Example: R8A7790 (R-Car H2) USB-DMACs - - usb_dmac0: dma-controller@e65a0000 { - compatible = "renesas,r8a7790-usb-dmac", "renesas,usb-dmac"; - reg = <0 0xe65a0000 0 0x100>; - interrupts = <0 109 IRQ_TYPE_LEVEL_HIGH - 0 109 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "ch0", "ch1"; - clocks = <&mstp3_clks R8A7790_CLK_USBDMAC0>; - #dma-cells = <1>; - dma-channels = <2>; - }; - - usb_dmac1: dma-controller@e65b0000 { - compatible = "renesas,usb-dmac"; - reg = <0 0xe65b0000 0 0x100>; - interrupts = <0 110 IRQ_TYPE_LEVEL_HIGH - 0 110 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "ch0", "ch1"; - clocks = <&mstp3_clks R8A7790_CLK_USBDMAC1>; - #dma-cells = <1>; - dma-channels = <2>; - }; diff --git a/dts/Bindings/dma/renesas,usb-dmac.yaml b/dts/Bindings/dma/renesas,usb-dmac.yaml new file mode 100644 index 0000000000..9ca6d8ddf2 --- /dev/null +++ b/dts/Bindings/dma/renesas,usb-dmac.yaml @@ -0,0 +1,102 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/dma/renesas,usb-dmac.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Renesas USB DMA Controller + +maintainers: + - Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> + +allOf: + - $ref: "dma-controller.yaml#" + +properties: + compatible: + items: + - enum: + - renesas,r8a7743-usb-dmac # RZ/G1M + - renesas,r8a7744-usb-dmac # RZ/G1N + - renesas,r8a7745-usb-dmac # RZ/G1E + - renesas,r8a77470-usb-dmac # RZ/G1C + - renesas,r8a774a1-usb-dmac # RZ/G2M + - renesas,r8a774b1-usb-dmac # RZ/G2N + - renesas,r8a774c0-usb-dmac # RZ/G2E + - renesas,r8a7790-usb-dmac # R-Car H2 + - renesas,r8a7791-usb-dmac # R-Car M2-W + - renesas,r8a7793-usb-dmac # R-Car M2-N + - renesas,r8a7794-usb-dmac # R-Car E2 + - renesas,r8a7795-usb-dmac # R-Car H3 + - renesas,r8a7796-usb-dmac # R-Car M3-W + - renesas,r8a77961-usb-dmac # R-Car M3-W+ + - renesas,r8a77965-usb-dmac # R-Car M3-N + - renesas,r8a77990-usb-dmac # R-Car E3 + - renesas,r8a77995-usb-dmac # R-Car D3 + - const: renesas,usb-dmac + + reg: + maxItems: 1 + + interrupts: + minItems: 2 + maxItems: 2 + + interrupt-names: + items: + - pattern: ch0 + - pattern: ch1 + + clocks: + maxItems: 1 + + '#dma-cells': + const: 1 + description: + The cell specifies the channel number of the DMAC port connected to + the DMA client. + + dma-channels: + const: 2 + + iommus: + minItems: 2 + maxItems: 2 + + power-domains: + maxItems: 1 + + resets: + maxItems: 1 + +required: + - compatible + - reg + - interrupts + - interrupt-names + - clocks + - '#dma-cells' + - dma-channels + - power-domains + - resets + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/r8a7790-cpg-mssr.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/power/r8a7790-sysc.h> + + usb_dmac0: dma-controller@e65a0000 { + compatible = "renesas,r8a7790-usb-dmac", "renesas,usb-dmac"; + reg = <0xe65a0000 0x100>; + interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "ch0", "ch1"; + clocks = <&cpg CPG_MOD 330>; + power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 330>; + #dma-cells = <1>; + dma-channels = <2>; + }; diff --git a/dts/Bindings/dma/sifive,fu540-c000-pdma.yaml b/dts/Bindings/dma/sifive,fu540-c000-pdma.yaml index e7f2ad7dab..d32a71b975 100644 --- a/dts/Bindings/dma/sifive,fu540-c000-pdma.yaml +++ b/dts/Bindings/dma/sifive,fu540-c000-pdma.yaml @@ -49,7 +49,7 @@ examples: - | dma@3000000 { compatible = "sifive,fu540-c000-pdma"; - reg = <0x0 0x3000000 0x0 0x8000>; + reg = <0x3000000 0x8000>; interrupts = <23 24 25 26 27 28 29 30>; #dma-cells = <1>; }; diff --git a/dts/Bindings/dma/st,stm32-dma.yaml b/dts/Bindings/dma/st,stm32-dma.yaml index 0c0ac11ad5..71987878e4 100644 --- a/dts/Bindings/dma/st,stm32-dma.yaml +++ b/dts/Bindings/dma/st,stm32-dma.yaml @@ -36,6 +36,11 @@ description: | 0x1: 1/2 full FIFO 0x2: 3/4 full FIFO 0x3: full FIFO + -bit 2: DMA direct mode + 0x0: FIFO mode with threshold selectable with bit 0-1 + 0x1: Direct mode: each DMA request immediately initiates a transfer + from/to the memory, FIFO is bypassed. + maintainers: - Amelie Delaunay <amelie.delaunay@st.com> diff --git a/dts/Bindings/dma/ti/k3-udma.yaml b/dts/Bindings/dma/ti/k3-udma.yaml index 39ea05e6e5..dd70ddab4f 100644 --- a/dts/Bindings/dma/ti/k3-udma.yaml +++ b/dts/Bindings/dma/ti/k3-udma.yaml @@ -69,34 +69,30 @@ properties: maxItems: 3 reg-names: - items: - - const: gcfg - - const: rchanrt - - const: tchanrt + items: + - const: gcfg + - const: rchanrt + - const: tchanrt msi-parent: true ti,sci: description: phandle to TI-SCI compatible System controller node - allOf: - - $ref: /schemas/types.yaml#/definitions/phandle + $ref: /schemas/types.yaml#/definitions/phandle ti,sci-dev-id: description: TI-SCI device id of UDMAP - allOf: - - $ref: /schemas/types.yaml#/definitions/uint32 + $ref: /schemas/types.yaml#/definitions/uint32 ti,ringacc: description: phandle to the ring accelerator node - allOf: - - $ref: /schemas/types.yaml#/definitions/phandle + $ref: /schemas/types.yaml#/definitions/phandle ti,sci-rm-range-tchan: description: | Array of UDMA tchan resource subtypes for resource allocation for this host - allOf: - - $ref: /schemas/types.yaml#/definitions/uint32-array + $ref: /schemas/types.yaml#/definitions/uint32-array minItems: 1 # Should be enough maxItems: 255 @@ -105,8 +101,7 @@ properties: description: | Array of UDMA rchan resource subtypes for resource allocation for this host - allOf: - - $ref: /schemas/types.yaml#/definitions/uint32-array + $ref: /schemas/types.yaml#/definitions/uint32-array minItems: 1 # Should be enough maxItems: 255 @@ -115,8 +110,7 @@ properties: description: | Array of UDMA rflow resource subtypes for resource allocation for this host - allOf: - - $ref: /schemas/types.yaml#/definitions/uint32-array + $ref: /schemas/types.yaml#/definitions/uint32-array minItems: 1 # Should be enough maxItems: 255 @@ -142,8 +136,7 @@ then: properties: ti,udma-atype: description: ATYPE value which should be used by non slave channels - allOf: - - $ref: /schemas/types.yaml#/definitions/uint32 + $ref: /schemas/types.yaml#/definitions/uint32 required: - ti,udma-atype |