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authorSascha Hauer <s.hauer@pengutronix.de>2022-10-18 11:24:12 +0200
committerSascha Hauer <s.hauer@pengutronix.de>2022-10-20 08:41:39 +0200
commit32e2176ba05083b66b7585d4ca81bcb5c5d72f84 (patch)
tree51b8628d96eb6415b11e2875dc6158f695af6573 /dts/Bindings/fpga
parent044294bdbee9e7ef8ffc5c3a9ef7841a09a84ff7 (diff)
downloadbarebox-32e2176ba05083b66b7585d4ca81bcb5c5d72f84.tar.gz
barebox-32e2176ba05083b66b7585d4ca81bcb5c5d72f84.tar.xz
dts: update to v6.1-rc1
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'dts/Bindings/fpga')
-rw-r--r--dts/Bindings/fpga/microchip,mpf-spi-fpga-mgr.yaml7
-rw-r--r--dts/Bindings/fpga/xilinx-zynq-fpga-mgr.yaml2
-rw-r--r--dts/Bindings/fpga/xlnx,zynqmp-pcap-fpga.yaml2
3 files changed, 6 insertions, 5 deletions
diff --git a/dts/Bindings/fpga/microchip,mpf-spi-fpga-mgr.yaml b/dts/Bindings/fpga/microchip,mpf-spi-fpga-mgr.yaml
index aee45cb155..527532f039 100644
--- a/dts/Bindings/fpga/microchip,mpf-spi-fpga-mgr.yaml
+++ b/dts/Bindings/fpga/microchip,mpf-spi-fpga-mgr.yaml
@@ -22,13 +22,14 @@ properties:
description: SPI chip select
maxItems: 1
- spi-max-frequency: true
-
required:
- compatible
- reg
-additionalProperties: false
+allOf:
+ - $ref: /schemas/spi/spi-peripheral-props.yaml#
+
+unevaluatedProperties: false
examples:
- |
diff --git a/dts/Bindings/fpga/xilinx-zynq-fpga-mgr.yaml b/dts/Bindings/fpga/xilinx-zynq-fpga-mgr.yaml
index 29daca4be4..f47b6140a7 100644
--- a/dts/Bindings/fpga/xilinx-zynq-fpga-mgr.yaml
+++ b/dts/Bindings/fpga/xilinx-zynq-fpga-mgr.yaml
@@ -4,7 +4,7 @@
$id: http://devicetree.org/schemas/fpga/xilinx-zynq-fpga-mgr.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
-title: Xilinx Zynq FPGA Manager Device Tree Bindings
+title: Xilinx Zynq FPGA Manager
maintainers:
- Michal Simek <michal.simek@xilinx.com>
diff --git a/dts/Bindings/fpga/xlnx,zynqmp-pcap-fpga.yaml b/dts/Bindings/fpga/xlnx,zynqmp-pcap-fpga.yaml
index 6cd2bdc06b..00a8d92ff7 100644
--- a/dts/Bindings/fpga/xlnx,zynqmp-pcap-fpga.yaml
+++ b/dts/Bindings/fpga/xlnx,zynqmp-pcap-fpga.yaml
@@ -4,7 +4,7 @@
$id: http://devicetree.org/schemas/fpga/xlnx,zynqmp-pcap-fpga.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
-title: Xilinx Zynq Ultrascale MPSoC FPGA Manager Device Tree Bindings
+title: Xilinx Zynq Ultrascale MPSoC FPGA Manager
maintainers:
- Nava kishore Manne <navam@xilinx.com>