summaryrefslogtreecommitdiffstats
path: root/dts/Bindings/interrupt-controller/amazon,al-fic.txt
diff options
context:
space:
mode:
authorSascha Hauer <s.hauer@pengutronix.de>2019-08-19 08:56:20 +0200
committerSascha Hauer <s.hauer@pengutronix.de>2019-08-19 08:56:20 +0200
commit6940ba22c66ac1c713500027bf5f6832442a1410 (patch)
treea460f01b9807e1c17206a40dbc94b6f54167cf29 /dts/Bindings/interrupt-controller/amazon,al-fic.txt
parente66a790177410d7433e6672d97bb0b54455ba669 (diff)
downloadbarebox-6940ba22c66ac1c713500027bf5f6832442a1410.tar.gz
barebox-6940ba22c66ac1c713500027bf5f6832442a1410.tar.xz
dts: update to v5.3-rc1
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'dts/Bindings/interrupt-controller/amazon,al-fic.txt')
-rw-r--r--dts/Bindings/interrupt-controller/amazon,al-fic.txt29
1 files changed, 29 insertions, 0 deletions
diff --git a/dts/Bindings/interrupt-controller/amazon,al-fic.txt b/dts/Bindings/interrupt-controller/amazon,al-fic.txt
new file mode 100644
index 0000000000..4e82fd575c
--- /dev/null
+++ b/dts/Bindings/interrupt-controller/amazon,al-fic.txt
@@ -0,0 +1,29 @@
+Amazon's Annapurna Labs Fabric Interrupt Controller
+
+Required properties:
+
+- compatible: should be "amazon,al-fic"
+- reg: physical base address and size of the registers
+- interrupt-controller: identifies the node as an interrupt controller
+- #interrupt-cells: must be 2.
+ First cell defines the index of the interrupt within the controller.
+ Second cell is used to specify the trigger type and must be one of the
+ following:
+ - bits[3:0] trigger type and level flags
+ 1 = low-to-high edge triggered
+ 4 = active high level-sensitive
+- interrupt-parent: specifies the parent interrupt controller.
+- interrupts: describes which input line in the interrupt parent, this
+ fic's output is connected to. This field property depends on the parent's
+ binding
+
+Example:
+
+amazon_fic: interrupt-controller@0xfd8a8500 {
+ compatible = "amazon,al-fic";
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ reg = <0x0 0xfd8a8500 0x0 0x1000>;
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_SPI 0x0 IRQ_TYPE_LEVEL_HIGH>;
+};