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authorSascha Hauer <s.hauer@pengutronix.de>2015-12-08 07:35:17 +0100
committerSascha Hauer <s.hauer@pengutronix.de>2015-12-10 08:48:40 +0100
commit6e6d9a2ff045f09d5a03e876becea5e6a1dabe90 (patch)
treebcf5e71df4472e374d03cc15ca22b4f841d9c73d /dts/Bindings/interrupt-controller/intel,ce4100-ioapic.txt
parent8e2fd5380a4fd7cee428513dc8eab068912b49f1 (diff)
downloadbarebox-6e6d9a2ff045f09d5a03e876becea5e6a1dabe90.tar.gz
dts: update to v4.4-rc1
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'dts/Bindings/interrupt-controller/intel,ce4100-ioapic.txt')
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+Interrupt chips
+---------------
+
+* Intel I/O Advanced Programmable Interrupt Controller (IO APIC)
+
+ Required properties:
+ --------------------
+ compatible = "intel,ce4100-ioapic";
+ #interrupt-cells = <2>;
+
+ Device's interrupt property:
+
+ interrupts = <P S>;
+
+ The first number (P) represents the interrupt pin which is wired to the
+ IO APIC. The second number (S) represents the sense of interrupt which
+ should be configured and can be one of:
+ 0 - Edge Rising
+ 1 - Level Low
+ 2 - Level High
+ 3 - Edge Falling
+
+* Local APIC
+ Required property:
+
+ compatible = "intel,ce4100-lapic";