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authorSascha Hauer <s.hauer@pengutronix.de>2019-04-05 14:51:50 +0200
committerSascha Hauer <s.hauer@pengutronix.de>2019-04-08 10:16:55 +0200
commit1dc748b3b202cadf9b799874d9af8d441ee556bc (patch)
tree58fd3c90a40e2d0128b0c7f36d63d7fc126bb20d /dts/Bindings/iommu
parent9688b49cd3bc0b61a019e8e1311236c9975a0777 (diff)
downloadbarebox-1dc748b3b202cadf9b799874d9af8d441ee556bc.tar.gz
barebox-1dc748b3b202cadf9b799874d9af8d441ee556bc.tar.xz
dts: update to v5.1-rc1
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'dts/Bindings/iommu')
-rw-r--r--dts/Bindings/iommu/nvidia,tegra20-gart.txt14
1 files changed, 0 insertions, 14 deletions
diff --git a/dts/Bindings/iommu/nvidia,tegra20-gart.txt b/dts/Bindings/iommu/nvidia,tegra20-gart.txt
deleted file mode 100644
index 099d9362eb..0000000000
--- a/dts/Bindings/iommu/nvidia,tegra20-gart.txt
+++ /dev/null
@@ -1,14 +0,0 @@
-NVIDIA Tegra 20 GART
-
-Required properties:
-- compatible: "nvidia,tegra20-gart"
-- reg: Two pairs of cells specifying the physical address and size of
- the memory controller registers and the GART aperture respectively.
-
-Example:
-
- gart {
- compatible = "nvidia,tegra20-gart";
- reg = <0x7000f024 0x00000018 /* controller registers */
- 0x58000000 0x02000000>; /* GART aperture */
- };