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| author | Sascha Hauer <s.hauer@pengutronix.de> | 2020-08-17 08:16:38 +0200 |
|---|---|---|
| committer | Sascha Hauer <s.hauer@pengutronix.de> | 2020-08-17 09:51:44 +0200 |
| commit | 0c2e2b7d8fd795c24abc7bfd3752eb3e366155eb (patch) | |
| tree | 21cddf4b49891b7df21cbe5e5dd358d4e44e031d /dts/Bindings/memory-controllers/fsl/mmdc.yaml | |
| parent | 8ef08db9ad225acbf7326493cc586bb14fd917f5 (diff) | |
| download | barebox-0c2e2b7d8fd795c24abc7bfd3752eb3e366155eb.tar.gz barebox-0c2e2b7d8fd795c24abc7bfd3752eb3e366155eb.tar.xz | |
dts: update to v5.9-rc1
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'dts/Bindings/memory-controllers/fsl/mmdc.yaml')
| -rw-r--r-- | dts/Bindings/memory-controllers/fsl/mmdc.yaml | 49 |
1 files changed, 49 insertions, 0 deletions
diff --git a/dts/Bindings/memory-controllers/fsl/mmdc.yaml b/dts/Bindings/memory-controllers/fsl/mmdc.yaml new file mode 100644 index 0000000000..68484136a5 --- /dev/null +++ b/dts/Bindings/memory-controllers/fsl/mmdc.yaml @@ -0,0 +1,49 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/memory-controllers/fsl/mmdc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Freescale Multi Mode DDR controller (MMDC) + +maintainers: + - Anson Huang <Anson.Huang@nxp.com> + +properties: + compatible: + oneOf: + - const: fsl,imx6q-mmdc + - items: + - enum: + - fsl,imx6qp-mmdc + - fsl,imx6sl-mmdc + - fsl,imx6sll-mmdc + - fsl,imx6sx-mmdc + - fsl,imx6ul-mmdc + - fsl,imx7ulp-mmdc + - const: fsl,imx6q-mmdc + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + +required: + - compatible + - reg + +examples: + - | + #include <dt-bindings/clock/imx6qdl-clock.h> + + memory-controller@21b0000 { + compatible = "fsl,imx6q-mmdc"; + reg = <0x021b0000 0x4000>; + clocks = <&clks IMX6QDL_CLK_MMDC_P0_IPG>; + }; + + memory-controller@21b4000 { + compatible = "fsl,imx6q-mmdc"; + reg = <0x021b4000 0x4000>; + }; |