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authorSascha Hauer <s.hauer@pengutronix.de>2015-05-06 08:56:43 +0200
committerSascha Hauer <s.hauer@pengutronix.de>2015-05-06 08:56:43 +0200
commit461f8cfc7ea788428240271818363333ceff5c4c (patch)
treea3d6e3737c203ea29f8db2a6ddaadc326247376c /dts/Bindings/mmc/exynos-dw-mshc.txt
parent6345d37ae50c3ac8dd0e6176bc846fe211cbddd4 (diff)
downloadbarebox-461f8cfc7ea788428240271818363333ceff5c4c.tar.gz
barebox-461f8cfc7ea788428240271818363333ceff5c4c.tar.xz
dts: update to v4.1-rc1
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'dts/Bindings/mmc/exynos-dw-mshc.txt')
-rw-r--r--dts/Bindings/mmc/exynos-dw-mshc.txt7
1 files changed, 7 insertions, 0 deletions
diff --git a/dts/Bindings/mmc/exynos-dw-mshc.txt b/dts/Bindings/mmc/exynos-dw-mshc.txt
index ee4fc0576c..aad9844278 100644
--- a/dts/Bindings/mmc/exynos-dw-mshc.txt
+++ b/dts/Bindings/mmc/exynos-dw-mshc.txt
@@ -36,6 +36,8 @@ Required Properties:
in transmit mode and CIU clock phase shift value in receive mode for double
data rate mode operation. Refer notes below for the order of the cells and the
valid values.
+* samsung,dw-mshc-hs400-timing: Specifies the value of CIU TX and RX clock phase
+ shift value for hs400 mode operation.
Notes for the sdr-timing and ddr-timing values:
@@ -50,6 +52,9 @@ Required Properties:
- if CIU clock divider value is 0 (that is divide by 1), both tx and rx
phase shift clocks should be 0.
+* samsung,read-strobe-delay: RCLK (Data strobe) delay to control HS400 mode
+ (Latency value for delay line in Read path)
+
Required properties for a slot (Deprecated - Recommend to use one slot per host):
* gpios: specifies a list of gpios used for command, clock and data bus. The
@@ -82,5 +87,7 @@ Example:
samsung,dw-mshc-ciu-div = <3>;
samsung,dw-mshc-sdr-timing = <2 3>;
samsung,dw-mshc-ddr-timing = <1 2>;
+ samsung,dw-mshc-hs400-timing = <0 2>;
+ samsung,read-strobe-delay = <90>;
bus-width = <8>;
};