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author | Sascha Hauer <s.hauer@pengutronix.de> | 2017-11-28 11:02:14 +0100 |
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committer | Sascha Hauer <s.hauer@pengutronix.de> | 2017-11-28 11:06:44 +0100 |
commit | 2e9cce8fb1f577088e2b20ae2f461130e13ad190 (patch) | |
tree | f82ae53e88d36e07608be1b3159da296ed025ef1 /dts/Bindings/mtd | |
parent | c68d466d263827692aa809e6b34abb90a1cab515 (diff) | |
download | barebox-2e9cce8fb1f577088e2b20ae2f461130e13ad190.tar.gz barebox-2e9cce8fb1f577088e2b20ae2f461130e13ad190.tar.xz |
dts: update to v4.15-rc1
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'dts/Bindings/mtd')
-rw-r--r-- | dts/Bindings/mtd/cadence-quadspi.txt | 7 | ||||
-rw-r--r-- | dts/Bindings/mtd/denali-nand.txt | 2 | ||||
-rw-r--r-- | dts/Bindings/mtd/jedec,spi-nor.txt | 3 | ||||
-rw-r--r-- | dts/Bindings/mtd/mtk-quadspi.txt | 15 | ||||
-rw-r--r-- | dts/Bindings/mtd/pxa3xx-nand.txt | 4 | ||||
-rw-r--r-- | dts/Bindings/mtd/sunxi-nand.txt | 2 |
6 files changed, 24 insertions, 9 deletions
diff --git a/dts/Bindings/mtd/cadence-quadspi.txt b/dts/Bindings/mtd/cadence-quadspi.txt index f248056da2..bb2075df9b 100644 --- a/dts/Bindings/mtd/cadence-quadspi.txt +++ b/dts/Bindings/mtd/cadence-quadspi.txt @@ -1,7 +1,9 @@ * Cadence Quad SPI controller Required properties: -- compatible : Should be "cdns,qspi-nor". +- compatible : should be one of the following: + Generic default - "cdns,qspi-nor". + For TI 66AK2G SoC - "ti,k2g-qspi", "cdns,qspi-nor". - reg : Contains two entries, each of which is a tuple consisting of a physical address and length. The first entry is the address and length of the controller register set. The second entry is the @@ -14,6 +16,9 @@ Required properties: Optional properties: - cdns,is-decoded-cs : Flag to indicate whether decoder is used or not. +- cdns,rclk-en : Flag to indicate that QSPI return clock is used to latch + the read data rather than the QSPI clock. Make sure that QSPI return + clock is populated on the board before using this property. Optional subnodes: Subnodes of the Cadence Quad SPI controller are spi slave nodes with additional diff --git a/dts/Bindings/mtd/denali-nand.txt b/dts/Bindings/mtd/denali-nand.txt index 504291d2e5..0ee8edb60e 100644 --- a/dts/Bindings/mtd/denali-nand.txt +++ b/dts/Bindings/mtd/denali-nand.txt @@ -29,7 +29,7 @@ nand: nand@ff900000 { #address-cells = <1>; #size-cells = <1>; compatible = "altr,socfpga-denali-nand"; - reg = <0xff900000 0x100000>, <0xffb80000 0x10000>; + reg = <0xff900000 0x20>, <0xffb80000 0x1000>; reg-names = "nand_data", "denali_reg"; interrupts = <0 144 4>; }; diff --git a/dts/Bindings/mtd/jedec,spi-nor.txt b/dts/Bindings/mtd/jedec,spi-nor.txt index 9ce35af850..376fa2f50e 100644 --- a/dts/Bindings/mtd/jedec,spi-nor.txt +++ b/dts/Bindings/mtd/jedec,spi-nor.txt @@ -13,6 +13,8 @@ Required properties: at25df321a at25df641 at26df081a + en25s64 + mr25h128 mr25h256 mr25h10 mr25h40 @@ -31,6 +33,7 @@ Required properties: s25fl008k s25fl064k sst25vf040b + sst25wf040b m25p40 m25p80 m25p16 diff --git a/dts/Bindings/mtd/mtk-quadspi.txt b/dts/Bindings/mtd/mtk-quadspi.txt index 840f9405dc..56d3668e2c 100644 --- a/dts/Bindings/mtd/mtk-quadspi.txt +++ b/dts/Bindings/mtd/mtk-quadspi.txt @@ -1,13 +1,16 @@ * Serial NOR flash controller for MTK MT81xx (and similar) Required properties: -- compatible: The possible values are: - "mediatek,mt2701-nor" - "mediatek,mt7623-nor" +- compatible: For mt8173, compatible should be "mediatek,mt8173-nor", + and it's the fallback compatible for other Soc. + For every other SoC, should contain both the SoC-specific compatible + string and "mediatek,mt8173-nor". + The possible values are: + "mediatek,mt2701-nor", "mediatek,mt8173-nor" + "mediatek,mt2712-nor", "mediatek,mt8173-nor" + "mediatek,mt7622-nor", "mediatek,mt8173-nor" + "mediatek,mt7623-nor", "mediatek,mt8173-nor" "mediatek,mt8173-nor" - For mt8173, compatible should be "mediatek,mt8173-nor". - For every other SoC, should contain both the SoC-specific compatible string - and "mediatek,mt8173-nor". - reg: physical base address and length of the controller's register - clocks: the phandle of the clocks needed by the nor controller - clock-names: the names of the clocks diff --git a/dts/Bindings/mtd/pxa3xx-nand.txt b/dts/Bindings/mtd/pxa3xx-nand.txt index d9b655f110..d4ee4da584 100644 --- a/dts/Bindings/mtd/pxa3xx-nand.txt +++ b/dts/Bindings/mtd/pxa3xx-nand.txt @@ -5,9 +5,13 @@ Required properties: - compatible: Should be set to one of the following: marvell,pxa3xx-nand marvell,armada370-nand + marvell,armada-8k-nand - reg: The register base for the controller - interrupts: The interrupt to map - #address-cells: Set to <1> if the node includes partitions + - marvell,system-controller: Set to retrieve the syscon node that handles + NAND controller related registers (only required + with marvell,armada-8k-nand compatible). Optional properties: diff --git a/dts/Bindings/mtd/sunxi-nand.txt b/dts/Bindings/mtd/sunxi-nand.txt index a37c67bcb4..5e13a5cdff 100644 --- a/dts/Bindings/mtd/sunxi-nand.txt +++ b/dts/Bindings/mtd/sunxi-nand.txt @@ -31,7 +31,7 @@ see Documentation/devicetree/bindings/mtd/nand.txt for generic bindings. Examples: -nfc: nand@01c03000 { +nfc: nand@1c03000 { compatible = "allwinner,sun4i-a10-nand"; reg = <0x01c03000 0x1000>; interrupts = <0 37 1>; |