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| author | Sascha Hauer <s.hauer@pengutronix.de> | 2019-08-19 08:56:20 +0200 |
|---|---|---|
| committer | Sascha Hauer <s.hauer@pengutronix.de> | 2019-08-19 08:56:20 +0200 |
| commit | 6940ba22c66ac1c713500027bf5f6832442a1410 (patch) | |
| tree | a460f01b9807e1c17206a40dbc94b6f54167cf29 /dts/Bindings/net/socfpga-dwmac.txt | |
| parent | e66a790177410d7433e6672d97bb0b54455ba669 (diff) | |
| download | barebox-6940ba22c66ac1c713500027bf5f6832442a1410.tar.gz barebox-6940ba22c66ac1c713500027bf5f6832442a1410.tar.xz | |
dts: update to v5.3-rc1
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'dts/Bindings/net/socfpga-dwmac.txt')
| -rw-r--r-- | dts/Bindings/net/socfpga-dwmac.txt | 10 |
1 files changed, 8 insertions, 2 deletions
diff --git a/dts/Bindings/net/socfpga-dwmac.txt b/dts/Bindings/net/socfpga-dwmac.txt index 17d6819669..612a8e8abc 100644 --- a/dts/Bindings/net/socfpga-dwmac.txt +++ b/dts/Bindings/net/socfpga-dwmac.txt @@ -6,11 +6,17 @@ present in Documentation/devicetree/bindings/net/stmmac.txt. The device node has additional properties: Required properties: - - compatible : Should contain "altr,socfpga-stmmac" along with - "snps,dwmac" and any applicable more detailed + - compatible : For Cyclone5/Arria5 SoCs it should contain + "altr,socfpga-stmmac". For Arria10/Agilex/Stratix10 SoCs + "altr,socfpga-stmmac-a10-s10". + Along with "snps,dwmac" and any applicable more detailed designware version numbers documented in stmmac.txt - altr,sysmgr-syscon : Should be the phandle to the system manager node that encompasses the glue register, the register offset, and the register shift. + On Cyclone5/Arria5, the register shift represents the PHY mode bits, while + on the Arria10/Stratix10/Agilex platforms, the register shift represents + bit for each emac to enable/disable signals from the FPGA fabric to the + EMAC modules. - altr,f2h_ptp_ref_clk use f2h_ptp_ref_clk instead of default eosc1 clock for ptp ref clk. This affects all emacs as the clock is common. |