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| author | Sascha Hauer <s.hauer@pengutronix.de> | 2019-08-19 08:56:20 +0200 |
|---|---|---|
| committer | Sascha Hauer <s.hauer@pengutronix.de> | 2019-08-19 08:56:20 +0200 |
| commit | 6940ba22c66ac1c713500027bf5f6832442a1410 (patch) | |
| tree | a460f01b9807e1c17206a40dbc94b6f54167cf29 /dts/Bindings/pci/mobiveil-pcie.txt | |
| parent | e66a790177410d7433e6672d97bb0b54455ba669 (diff) | |
| download | barebox-6940ba22c66ac1c713500027bf5f6832442a1410.tar.gz barebox-6940ba22c66ac1c713500027bf5f6832442a1410.tar.xz | |
dts: update to v5.3-rc1
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'dts/Bindings/pci/mobiveil-pcie.txt')
| -rw-r--r-- | dts/Bindings/pci/mobiveil-pcie.txt | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/dts/Bindings/pci/mobiveil-pcie.txt b/dts/Bindings/pci/mobiveil-pcie.txt index a618d4787d..64156993e0 100644 --- a/dts/Bindings/pci/mobiveil-pcie.txt +++ b/dts/Bindings/pci/mobiveil-pcie.txt @@ -10,8 +10,10 @@ Required properties: interrupt source. The value must be 1. - compatible: Should contain "mbvl,gpex40-pcie" - reg: Should contain PCIe registers location and length + Mandatory: "config_axi_slave": PCIe controller registers "csr_axi_slave" : Bridge config registers + Optional: "gpio_slave" : GPIO registers to control slot power "apb_csr" : MSI registers |