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author | Sascha Hauer <s.hauer@pengutronix.de> | 2015-02-09 08:45:25 +0100 |
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committer | Sascha Hauer <s.hauer@pengutronix.de> | 2015-02-11 09:50:08 +0100 |
commit | ab001302c8e1718110bb8839c270d2caa817b214 (patch) | |
tree | f5ab4feb5242e548917c3536b8510080df9a4e8f /dts/Bindings/phy/samsung-phy.txt | |
parent | c937ef5d34ede89ae382cfe6d98ba366859a65af (diff) | |
download | barebox-ab001302c8e1718110bb8839c270d2caa817b214.tar.gz barebox-ab001302c8e1718110bb8839c270d2caa817b214.tar.xz |
dts: update to v3.19-rc1
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'dts/Bindings/phy/samsung-phy.txt')
-rw-r--r-- | dts/Bindings/phy/samsung-phy.txt | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/dts/Bindings/phy/samsung-phy.txt b/dts/Bindings/phy/samsung-phy.txt index 15e0f2c713..d5bad92082 100644 --- a/dts/Bindings/phy/samsung-phy.txt +++ b/dts/Bindings/phy/samsung-phy.txt @@ -128,6 +128,7 @@ Required properties: - compatible : Should be set to one of the following supported values: - "samsung,exynos5250-usbdrd-phy" - for exynos5250 SoC, - "samsung,exynos5420-usbdrd-phy" - for exynos5420 SoC. + - "samsung,exynos7-usbdrd-phy" - for exynos7 SoC. - reg : Register offset and length of USB DRD PHY register set; - clocks: Clock IDs array as required by the controller - clock-names: names of clocks correseponding to IDs in the clock property; @@ -138,6 +139,11 @@ Required properties: PHY operations, associated by phy name. It is used to determine bit values for clock settings register. For Exynos5420 this is given as 'sclk_usbphy30' in CMU. + - optional clocks: Exynos7 SoC has now following additional + gate clocks available: + - phy_pipe: for PIPE3 phy + - phy_utmi: for UTMI+ phy + - itp: for ITP generation - samsung,pmu-syscon: phandle for PMU system controller interface, used to control pmu registers for power isolation. - #phy-cells : from the generic PHY bindings, must be 1; |