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author | Sascha Hauer <s.hauer@pengutronix.de> | 2022-10-18 11:24:12 +0200 |
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committer | Sascha Hauer <s.hauer@pengutronix.de> | 2022-10-20 08:41:39 +0200 |
commit | 32e2176ba05083b66b7585d4ca81bcb5c5d72f84 (patch) | |
tree | 51b8628d96eb6415b11e2875dc6158f695af6573 /dts/Bindings/phy/ti,phy-gmii-sel.yaml | |
parent | 044294bdbee9e7ef8ffc5c3a9ef7841a09a84ff7 (diff) | |
download | barebox-32e2176ba05083b66b7585d4ca81bcb5c5d72f84.tar.gz barebox-32e2176ba05083b66b7585d4ca81bcb5c5d72f84.tar.xz |
dts: update to v6.1-rc1
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'dts/Bindings/phy/ti,phy-gmii-sel.yaml')
-rw-r--r-- | dts/Bindings/phy/ti,phy-gmii-sel.yaml | 27 |
1 files changed, 26 insertions, 1 deletions
diff --git a/dts/Bindings/phy/ti,phy-gmii-sel.yaml b/dts/Bindings/phy/ti,phy-gmii-sel.yaml index ff8a6d9eb1..da7cac537e 100644 --- a/dts/Bindings/phy/ti,phy-gmii-sel.yaml +++ b/dts/Bindings/phy/ti,phy-gmii-sel.yaml @@ -53,12 +53,25 @@ properties: - ti,am43xx-phy-gmii-sel - ti,dm814-phy-gmii-sel - ti,am654-phy-gmii-sel + - ti,j7200-cpsw5g-phy-gmii-sel reg: maxItems: 1 '#phy-cells': true + ti,qsgmii-main-ports: + $ref: /schemas/types.yaml#/definitions/uint32-array + description: | + Required only for QSGMII mode. Array to select the port for + QSGMII main mode. Rest of the ports are selected as QSGMII_SUB + ports automatically. Any one of the 4 CPSW5G ports can act as the + main port with the rest of them being the QSGMII_SUB ports. + maxItems: 1 + items: + minimum: 1 + maximum: 4 + allOf: - if: properties: @@ -73,6 +86,18 @@ allOf: '#phy-cells': const: 1 description: CPSW port number (starting from 1) + + - if: + not: + properties: + compatible: + contains: + enum: + - ti,j7200-cpsw5g-phy-gmii-sel + then: + properties: + ti,qsgmii-main-ports: false + - if: properties: compatible: @@ -97,7 +122,7 @@ additionalProperties: false examples: - | - phy_gmii_sel: phy-gmii-sel@650 { + phy_gmii_sel: phy@650 { compatible = "ti,am3352-phy-gmii-sel"; reg = <0x650 0x4>; #phy-cells = <2>; |